• AD9481 - Vref Capacitance

    The AD9481 datasheet mentions that a 10 uF bulk capacitor is required on the VREF pin when the internal fixed reference is used. It doesn't say what the maximum ESR for this capacitor should be. Is there a recommendation on how high the ESR can be for…

  • Interleaving two AD9481 application

    I have two questions about "INTERLEAVING TWO AD9481s ". The datasheet shows the
    description as below figure shown:
    1. The phase offset between two ADCs' Clock should be 180 degree, isn't it?
    2. How we deal with the two ADCs' DS…

  • 关于AD9481的数据转换输出问题

    AD9481芯片在使用过程中,数据同步时钟信号输出正常。在数据输出时钟信号正常的情况下,出现了下面的问题:

    当检测电压超出转换范围内时,输出全是0或全是1,这种情况下数据输出与期望输出相符,正常无问题。

    但是当电压在转换范围内的情况下数据输出引脚出现高阻态,数据输出与期望输出完全不符,不正常。

    这款芯片的控制引脚也不多,排查了一编,也没发现什么异常,请问这样的问题是出在哪里了?

  • RE: Hi-Z state of AD9481 outputs

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • RE: 关于AD9481工作在单端输入模式下的接法,望指导。

    This question has been closed by the EZ team and is assumed answered.
  • AD9481 CMOS customer board Rev.A Gerber files

    Where to get Gerber files for AD9481 CMOS customer board Rev.A PCB from the data sheet http://www.analog.com/media/en/technical-documentation/data-sheets/AD9481.pdf  (pp.26-27) ?

  • Strange Behavior of AD9481

    I am designing a laser ranger where the latency of the ADC matters. The ADC is clocked at 250MHz. According to the datasheet, the latency should be 8 clock cycles. Here is the problem: after every the latency changes randomly. Sometimes it is 8 cycles…

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