FAQ
Hello,
Our customer has question on the AD9446, please see below.
We are using the Analog AD9446BSVZ-100 ADC with LVDS outputs for this project.. Both the data bus outputs
And the clock output have the same timing range (2.1ns – 4.8ns).
两片AD9446-100同时采集正弦信号,采用内部参考电压,两路信号放大电路和两片AD外围电路全部相同。主芯片使用FPGA。
上电测试,由信号发生器输入两路正弦信号,频率10MHz,无相位差。
由SignalTap II 采集数据显示,第一片AD输入信号峰峰值约3700mV时,输出饱和(65536);第二片AD输入信号峰峰值约530mV时,输出饱和(65536)。
SENSE脚接地;实测VREF脚电压为1.58V和1.60V(排除参考电压的因素)。
调整信号发生器输入两路正弦信号的幅值、频率…
Hello
Is there recommended supply-sequence of AD9446 about AVDD1, AVDD2 and DRVDD?
I can not find supply sequence of AVDD1, AVDD2 and DRVDD in absolute maximum rating of datasheet.
I will use the sequence of AVDD2 (5V) --> AVDD1(3.3V) --> DRVDD…
请问:
选择COMS电平时,在没有通入信号的情况下,ADC9446的低八位全为高电平,通入信号以后,也一直保持不变,高八位跳变,但不符合输入信号的大体轮廓。
选择LVDS电平时,就不会出现以上情况,请问为什么?
@我的AD9446的工作在LVDS模式下,请问对于AD9446(100MHz),LVDS信号线的PCB走线的差分对的对间等长有没有要求?(PS:16对差分线,都做等长好复杂)谢谢!analogchina-adminhdx2FormerMemberAnalog1ezchinatest1122
I have two questions with AD9446.
1. What the meaning of Input referred noise in AD9446's datasheet ?
2. I want to test the dynamic performance of AD9446 with signal generator Tektronix_AFG3252(14 bit resolution). How could I sep up the input signal…
我的板子上AD9446供电条件:模拟5V管脚接模拟A5V,模拟3.3V管脚接A3.3V,而A3.3V由A5V通过AMS1117-3.3转换而来,数字3.3V管脚接D3.3V;数字地和模拟地管脚共同接模拟地。全部上电情况下,测得A5V噪声很大(10-20mV),只有在断开A3.3V时才会使A5V恢复正常(2mV以内)。请问可能是什么原因造成的。
Hello,
I,m a young application engineer for LXT-Credence company.
I have design for a customer who wants to test infra red sensor, a loadboard.
As the sensor delivers an output analog signal, and contains 288x384 pixels, I decided to use an ADC to…