You will have to rewrite adsb_decode.c to use the correct devices for AD9371/5. You will also need much more decimation in the FPGA since the minimum rate of the AD9371/5 is well above 4 MHz used in that application.
The latest BSP supports ZCU102 and…
We are using two AD9371 with one AD9528 chip. For now, we have connected one AD9371.
Our problem is sysref is not coming from the AD9528 output channels. We have configured AD9528 channel 0 and channel 2 for AD9371 DEV_CLK and SYSREF. And at the same…
Otherwise, I confirm that the ad9371 reset is high using scope while configuring ad9371 spi. We haven't put a pull-up resistor with reset but it should be pulled up by fpga gpio before ad9371 initialize.
Are you matching TX and RX rates for AD9371? What profile are you using for AD9371?
What is the common mode voltage (Vcm) range of the SYSREF & SYNCIN inputs on the AD9371? Pg 8 of the datasheet specifies the SYSREF & SYNCIN Input voltage Min=825mV & Max=1675mV. Using Differential Threshold voltages of +/-100mV results in…
Please refer to below thread,
The driver supports the AD9371 and AD9375, by default it does not support the AD9370.
If you want to use this driver with the AD9370:
ID_AD9371 = 0x0001,
Refer to the below post:
We are designing a custom board with AD9371. It will not have Ethernet port. So, we do not intend to connect it via TES. Could you let us know if the I2C interface parts AD7291 and EPROM are required for the configuration of AD9371 in any way or can…