We are in the process of configuring the AD9364 from the external processor board (Beaglebone Black) The configuration and setup code on External processor board(BBB) will configure ad9364 board using SPI.
Ad9364 board consist of Artix 7 FPGA and ad…
Does the GUI auto detect how many ad9364s are connected? How will we use one GUI to access all AD9364s?
AD9364 is a 1x1 version of AD9361 (that is 2x2).
AD9361 in 1x1 should have the same power consumption as AD9364.
AD9364 is a SISO version of AD9361 2x2 MIMO. Please refer to the AD9364 datasheet specification tables for AD9361 SISO mode of operation.
1. Can I get a complete datasheet for the AD9364?
2. What are the sample rates for the ADC on the AD9364?
hi,Dragos, the initial error of ad9364 is caused by the Project ID, the chip AD9361 is same with AD9364?
We are working on a design for two ad9364's and we want to achieve interchip loopback. Rx data from one ad364 to be fed to TX of the second ad9364. We are using fmcomms5 design as reference for Virtex7 Vivado design.
Test condition 1:
If AD9361 worked , AD9364 as well should work fine. Are you seeing this issue on multiple boards with AD9364 ?
Only difference between the two will be the unused RF ports in AD9364 which should not cause this issue.
You can try testing with internal Bist…
I was wanting to find out if the AD9364 can be used in a pin-to-pin compatible configuration with the AD9361.
Initial layout was targeted using the AD9361 but we are now going with the AD9364. However with the AD9364 pins A1, A2 andfew others are VSSA…
You can download the design package file for AD9364,
In UG-673, please refer to SERIAL PERIPHERAL INTERFACE (SPI) section for reading and writing…