If AD9361 worked , AD9364 as well should work fine. Are you seeing this issue on multiple boards with AD9364 ?
Only difference between the two will be the unused RF ports in AD9364 which should not cause this issue.
You can try testing with internal Bist…
AD9364 is an Agile transceiver which gives RF to bits. AD9364 is Direct conversion architecture and output of AD9364 is in digital form.
Can you give more details on why you want to connect multiple BBP?
We are in the process of configuring the AD9364 from the external processor board (Beaglebone Black) The configuration and setup code on External processor board(BBB) will configure ad9364 board using SPI.
Ad9364 board consist of Artix 7 FPGA and ad…
Hello,
We are working on a design for two ad9364's and we want to achieve interchip loopback. Rx data from one ad364 to be fed to TX of the second ad9364. We are using fmcomms5 design as reference for Virtex7 Vivado design.
Test condition 1:
we…
We are using fmcomms2 boards to set up LVDS Full Duplex TDD.
We don't understand how the maximum data rate matches with the reference manual UG763 and other sources.
It says in the following two links (and there is also a limit in software) that…
Question moved to Design Support AD9361/AD9363/AD9364 group.Andrei
Dupe of: https://ez.analog.com/wide-band-rf-transceivers/design-support/f/q-a/107230/need-ad9364-configuration
Answering question on other thread.
-Travis
Hi,
The data of ad9364 is 12bit, and the input data of the interface is 16bit.I am using the ip of there is axi_ad9361, which supports AD9361, AD9363, ad9364. How to expand? Can you give me an example?
I was wanting to find out if the AD9364 can be used in a pin-to-pin compatible configuration with the AD9361.
Initial layout was targeted using the AD9361 but we are now going with the AD9364. However with the AD9364 pins A1, A2 andfew others are VSSA…
AD9364 is a SISO version of AD9361 2x2 MIMO. Please refer to the AD9364 datasheet specification tables for AD9361 SISO mode of operation.