• Related to AD9364 Transceiver

    In our design we use AD9364 Transceiver (LVDS MODE),Reference clock of 40MHZ provided. The maximum DATA_CLK rate is increased to 245.76 MHz in LVDS mode as per the UG.I want to know relation between DATACLOCK & SAMPLING CLOCK?, Will ADC inside RF transceiver…

  • ad9364 transceiver register gui

    So, I found the general structure software to configure the registers in the ad9361/4, but this not what is usually required.  It is fine to have the structure c code, but what we really need is a GUI or excel spread sheet that allows us to modify the…

  • AD9364 FPGA Reference Design

    Hello,

    I would like to ask a question about AD9364 Agile RF Transceiver.

    In our company, we would like to use this RF transceiver in our special cards (PCBs). We want to learn how to control the transceiver. I searched on the wiki page and EZ for whether…

  • AD9364 RX analog filter

    Hello!

    I'm looking for more information about the RX analog filter in the AD9364. It is not clear to me how sharp the transition is from pass band to stop band. Could not find anything in the datasheet or user manual.

    Any information about this ?

  • AD9364 - Toggling Sampling Rate between 24/48MHz

    I am using the following hardware setup:

    • Zedboard
    • FMCOMMS4

    I have been able to properly initialize the AD9364, and get/set the TX LO and sampling rate with the following functions

    • ad9361_init
    • ad9361_set_tx_lo_freq()
    • ad9361_set_tx_sampling_freq()

  • AD9364 - Synchronizing DATA_CLK to BBP clock domain

    I am using a Zedboard/FMCOMMS4 setup.

    I would like the DATA_CLK signal coming from the AD9364 to be synchronized with the clock domain coming from my BBP. Right now, it seems the only way to do this is to provide a REF_CLK signal through the SMA connector…

  • AD9364 calibration timeout

    Hi,

    We come across an issue and we find the calibration error following: 

    ---------------------------------------------------------------------

    Base Address is 0xE0006000.SPI INIT!

    Calibration TIMEOUT (0x5E, 0x80)

    Calibration TIMEOUT (0x244, 0x80)

  • HI How to port AD9364 driver to xilinx petalinux

    Hi Team,

    Could you help me port driver. I have modules AD-FMCOMMS-4 EBZ board and Xilinx Zinq Ultrascale HW-Z1-ZCU102.

    I have planing to port below drivers from ADI  git repo to my petalinux repo in build/tmp/work-shared/zynqmp-generic/kernel-source/drivers…

  • connect usb camera to pluto AD9364

    We are trying to make a stand alone application to capture and transmit photos through the Plutosdr (ADALM) kit. With this an FPGA embedded with a synthesized ARM, it can be used via the plutosdr-fw firmware found online by Analog Devices (github.com…

  • AD9364 AGC Operation -in detail

    Hi,

    Need your kind support to understand the overall Gain Control of AD9364.

    Our Case:

    We are trying to store the ADC samples in RX path. TxA and RxA are shorted here to perform transmission and reception. We have observed the output waveform through…