• AD9364/Z7020 TXNRX/ENABLE pins not controlling AD9364


    I am having trouble controlling the AD9364 ENSM using pin control level mode.

    The hardware is a Picozed SDR 1x1 SOM Rev.C running custom HDL IP and no-OS software integrated into a custom RTOS architecture. I am currently tesing with the SOM breakout…

  • RE: AD9364 : Tuning TX & RX FAILED! error

    Are you seeing the tuning failure intermittently or does it happen always for a particular board? Are you using the latest driver(are you using Linus or no-os)and HDL? Are you using LVDS or CMOS interface? What is the ref_ clk freq that you are giving…

  • Are the AD9361 and AD9364 drop-in interchangeable (except for no RX2 in the AD9364)?

    Are the AD9361 and AD9364 drop-in interchangeable (except for no RX2 in the AD9364)?

  • AD9364 CMOS line length matching requirement

    We are making a new board with AD9364. We are following the ADALM pluto reference design. We have seen special patterns on the CMOS data lines. Is it for length matching? What is the criteria for it? What is the maximum length permitted in CMOS mode?…

  • DDS-Core-LPC Init for AD9364

    The script here (https://github.com/analogdevicesinc/rfsom-box-gui/blob/master/tun_tap/restart_modem_gui.sh#L68) configures the AD9361 and the DDS-Core for TX. On the ADRV9364, the last two register writes fail. Should anything be altered in order to…

  • AD9364


    we are using AD9364 chip in our project.

    we set ENABLE pin high(pin status checked in oscilloscope by probing to AD9364 ENABLE pin) from BBP(here FPGA) so we expecting AD state be (TxNRx=0).

    But AD state is in continuously in Alert state(state 5).

  • AD9364 Received Frequency Carrier Offset

    what is the maximum frequency offset Receiver can demodulate from the tuned frequency of the Receiver?

  • RE: AD9364 CMOS mode interface


    Yes, you are correct. To Verify the FPGA-AD CMOS interface Loopback bist test is not working.

    ie, We are not able to see any output in the path of FPGA-AD-FPGA and also RX path AD->FPGA.


  • RE: AD9364

    Please generate a profile with the required sampling rate and BW using the matlab based filter wizard tool and then check if you are seeing the same behavior.