Hi ad9361 experts:
I am using ad9361 with FAGC mode. When I input different amplitude signal into the RX port of ad9361, I found that when the input signal is between -67~-72dBm, the device can not receive correct signal. But it works well when the input…
The device is unable to calibrate:
ad9361 spi32766.0: Calibration TIMEOUT (0x5E, 0x80)random: crng init donead9361 spi32766.0: Calibration TIMEOUT (0x247, 0x2)ad9361 spi32766.0: Calibration TIMEOUT (0x287, 0x2)ad9361 spi32766.0: Calibration TIMEOUT (0x247…
I am trying to understand the data interface to this chip. When in CMOS, dual port, half duplex mode; the BBP drives the ENABLE and the TXNRX lines. My understanding is that it asserts the enable high with TXNRX low to request any received data…
如果你说的是外部晶体, 而不是晶振, 则需要用到芯片内部的DCXO, 参考附件DCXO的应用文档
你说的无源外部"晶振", 应该是指单独的晶体吧(不带振荡电路的那种). 用晶体是需要配合芯片内部的DCXO才能正常工作的. 详见附件关于DCXO使用的文档。
AD9363 is really within the AD9361 family. AD9361 came first. AD9363 is really just a feature trimmed, cost optimzed version of the AD9361. 99% of the doc applies to both. The same driver and HDL is used on both.
Thanks for the info.
I did find the DDS inside the AD9361 block.
However, my self generated Device Tree does not contain the reference to the cf-ad9361-dds-core-lpc@79024000, as is the case with the ADI distributed version of this device…