I am trying to receive data from AD9287 with xilinx ZCU102 board.
Adc gives serial lvds output.
I am using iserdes to receive the data according to xapp524. I cannot get the right data from the xilinx catch.
Do you have an example to get the right…
Hello, i am trying to interface an AD9287 to my artix 7 device. Adc gives serial lvds output. I am using iserdes (selectio) module but the problem is i do not know exact starting time of adc output so there is word framing error. İ could not catch the…
I hope your project is going well. Is this question related to capturing AD9287 data with your Artix FPGA? If so, has the sample FPGA code discussed in another EngineerZone thread helped?
If you still need the AD9287 FCO data, we can work on…
I have gotten a problem with AD9287ABCPZ-100, as follows,
According to the Timing diagram of AD9287 ,when my input clock is 20Mhz, the frequency of dataout should be 80Mhz ,and the bit clock(DCO) should be 80Mhz ,frame clock(FCO) should be 20Mhz .
AD9287 stops operating if the clock signal is removed. It should start working again after a clock input is provided. I recommend issuing a soft reset to the AD9287 through SPI after clock is restored if you are experiencing problem with the ADC…
Our customer will use your AD9287-100EBZ and ML695(Xilinx).
But they cannot connect due to that there is put the difference type connectors.
So we need the transfer board in there I think.
We cannot use this…
signal chian: analog input-<AFE-<AD8334-<AD9287-100-<Xilinx FPGA.
Clock input:epson100M crystal oscillator from TI CDCV304 clock buffer.
1.8V analog and digital power all from TI TPS5430, analog and digital are from one supply…
The customer is using AD9287 EVM.
They would like to measure the signal that mixed DC. But EVM has capacitor for rejecting DC.
Is there any way to modify EVM input stage for accept DC level signal?
Thank you for your help as always.