Thank you for trying the AD9287. Would it help you to look at the FPGA source code that we use to capture data from the AD9287? This code is written for Xilinx Virtex4.
If you would like to look at this code, please let me know and I will email…
Thank you for using the AD9287.
I agree with what you state from the AD9287 datasheet timing diagram.
Would you please double-check the signals you are probing? I believe it is impossible for FCO frequency to be greater than DCO frequency,…
First of all, special thanks for your close interest.
Yes , it was related to AD9287. I had a chance to look at the code that you sent but I could not figure out why SPI_control module is not included to top module. Because I did not write the code…
AD9287 stops operating if the clock signal is removed. It should start working again after a clock input is provided. I recommend issuing a soft reset to the AD9287 through SPI after clock is restored if you are experiencing problem with the ADC…
Thank you for working with the AD9287 customer.
You already mentioned the CVT-ADC-FMC-INTPZB. This is what came to mind when I saw your question. I believe that CVT-ADC-FMC-INTPZB takes the AD9287 outputs to the appropriate FMC connector pins…
Thank you for your comment Rejeesh.
But on another removed sled your Doug posted the good idea.
Do you have a good idea for connection AD9287-100EBZ?
For the time being, I will report above idea to our customer.
The customer is using AD9287 EVM.
They would like to measure the signal that mixed DC. But EVM has capacitor for rejecting DC.
Is there any way to modify EVM input stage for accept DC level signal?
Thank you for your help as always.
signal chian: analog input-<AFE-<AD8334-<AD9287-100-<Xilinx FPGA.
Clock input:epson100M crystal oscillator from TI CDCV304 clock buffer.
1.8V analog and digital power all from TI TPS5430, analog and digital are from one supply…