Is it necessary to configure AD9271 when using it?
Now, I control AD9271 through FPGA, only DCO and FCO have clock output, but DOUTx has no output (a high level).
How can I solve this problem?
I am donig a capture test using the AD9271 ADC (25 MSPS variant) in my data acquistion system.For this I am appling a 1 MHz ac coupled 1Vpp sinewave to one channels of my AD9271.I am controling this ADC with an FPGA.Because I want to…
HI EVERYONE. MY QUESTION IS HOW I CAN ACCESS AD9271-BSVZ25 SPICE MODEL? I DIDN'T FIND PLEASE HELP ME. THANK YOU
I am interfacing the AD9271 to a Zynq Xilinx FPGA. Is there a reference Verilog or VHDL design to interface the LVDS Serdes out of the ADC into the FPGA?
The AD9271 requires a software transfer bit be written to latch the SPI writes into their registers. This is found in Register 0xFF, bit 0. It is self-clearing but does need to be written after all write commands.
I am doing a sinewave capture test using the AD9271 ADC (25 MSPS variant) in my data acquistion system. For this I am applying a 1MHz ac coupled 100mVpp sinewave to two channels of my AD9271, with the remaining six channels left unconnected…
This is about the differential DCO outputs from the AD9271. I am controlling this ADC with an FPGA. A 10 MHz signal is sent to the CLK pins, using the Figure 58. Single Ended circuit given by the datasheet.
When I tried to collect the digital bits from…
Sorry, we provide only PDF form of schematics.
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