• AD9265 - Cannot access SPI when analog input ON.

    Hi all,

    I faced a strange issue about SPI of AD9265. I need to change some ADC register dynamically, but I can't when analog input signal is ON.

    AD9265 analog input port is connected to signal generator, and SPI port is connected to Zynq - Xilinx's…

  • AD9265 BIST

    Can you explain how the BIST works in the AD9265?  How do I perform it and what should I expect for a result?

  • RE: 关于DCO同步时钟的相关问题


  • Is Xilinx DMA compatible with libiio

    Hi, larsc,

    if attach a "xilinx dma" to a iio device(such as ad9265), is libiio compatible with it?

  • RE: Voltage offset differences under different sampling rates?! - AD9265

    Dear David:

         I have tested another high speed ADC, AD9226ARSZ, 12-Bit 65MSps, to compare with AD9265, but i didn't find the gain error of AD9226 in different sampling rate. From the datasheet of AD9226ARSZ, it has max. 2% FSR gain error. We analyzed…

  • RE: Do you have the foot print fig for CP-48-8?

    Hi Kaos-

    Since this discussion is about the AD9265 I have moved it to the High-Speed ADCs Community.  I checked on this and found that ADI no longer provides footprints for standalone packages.  Instead, each part number has a symbol and footprint that…

  • Is it possibe to evaluate LVDS outputs from AD9265 using Visual Analog ?

    I'm interested in using AD9562 in a research project. I have adquired AD9265-105EBZ and HSC-ADC-EVALCZ boards and I have obtained really good results using VisualAnalog. However my application requires to use AD9265 with LVDS outputs mode ( not supported…

  • RE: Verilog/VHDL for AD9265 Configuration via SPI

    Hello Wayne,

    We don't have a reference design with the use case you have in mind, for any of our projects at this time.

    We have an HDL reference design for AD9265 FMC at https://github.com/analogdevicesinc/hdl/tree/master/projects/ad9265_fmc which works…

  • RE: I got a question about ADRF6850 & AD9265 interface circuit

    Hi Sarah,

    The ADRF6850 will function with an output common mode level of 0.9V. But it is not supported by the datasheet and so will degrade some of the datasheet specifications such as P1dB. The typical output swing of the ADRF6850 is 2.5V p-p. With…

  • AD9265没有低位数据

    大家好,我设计了一版 AD9265+FPGA的采集板, AD9265的模拟与数字供电均通过磁珠与1.8V网络连接,AD9265的 DCO OR D0~D15 通过22欧姆电阻与FPGA直接连接(FPGA BANK电压也是1.8V)。 AD9265的差分时钟输入由FPGA提供(30MHz)。

    经过测量,AD9265的DCO输出是正常时钟,VREF 1.0V, VCOM 0.9V,然而对信号发生器的 100KHZ 300mVpp 进行采样并回传发现,正弦波被AD9265采样采集成了 多段台阶,也就是AD9265的大部分低位数据都是0…