If I understand your correctly, you intend on designing an external PLL circuit that generates the approximatley 640 MHz clock for the ADC (vs using its internal PLL clock syn).
If this is the case, you should wait for the external PLL to settle…
AD7626 could be a good candidate although it is not a sigma-delta type like the AD9260.
You may want to check the ADI website and do a parametric search to filter the product display base form your recommended specification.
Here are some ADCs that might help you start with, kindly see attched file.
Hello,Most of the sigma delta ADC's (like AD9260) are low pass hence they support signal bandwidths starting at DC to some upper limit (like 1.2 MHz with an oversampling ratio of 8 with FCLK=20SMSPS).
I would suggesting using a standard pipeline…
I have read the data sheet of AD9260, which said that the bias current is used by modulator amplifiers and flash preamplifiers. But I know AD9260 combined delta-sigma and pipeline and AD9629 only uses pipeline. So can you tell me more details…
I have bought an AD9269-80EBZ evaluation board for real time data capture application. I have a Xilinx Virtex 5 board and I want to interface AD9260 board with Virtex 5 for data acquisition. Can someone please provide me an example SPI programming…