FAQ
We plan to add a clock buffer/jitter cleaner chip in front of AD9239 clock input.
Could we use ADCLK905 chip? or you have other suggestion?
ADCLK905 use 3.3V while AD9239 use 1.8V power rails. Do you think it has an issue in the clock signal interface…
hi, the datasheet has clear instructions on how to bring up the device. if there is a capture error, most likely the link is not being correctly setup between the ADC and the logic device.
only one channel work,how can i to configure the ad,for details.thanks.
Hello,
100-Ohm resistor must be used on the CLK+/CLK- pins of AD9239?
Thank you,
K
Dear Sir/Madam
I wonder how to synchronize the eight channels' sample data. When PGM is enable, after the ADC output 66A5, what the sample delay will be
Thanks.
Hi!
my design used AD9239-210,input 200MHz clock,2 chip on the PCB,8 channels from the same clock sources.
after AD9239,data into FPGA through GTX.
(introduction in datasheet)
To minimize skew and time misalignment between eachchannel of the digital outputs…
hi,all
我现在用AD9239-250的芯片,参照咱们提供的设计进行操作,采用的是通过GTX接收数据,在接收数据后无法找到头帧头0xccaaddbb,还有点不明白,
1、0xccaaddbb是怎么配置下去的?
2、从时序图来看,AD9239输出的数据应该是8bit头+48bit data+8bit end这样的结构,在咱们的参考设计中却是需要寻找32bit的0xccaaddbb数据?
3、如果通过GTX接收数据时,怎么进行四个通道同步?
麻烦给尽快回复,最近项目比较紧急,多谢!