Hi ADI,

Is it possible to interleave the two ADCs on the AD9234 to achieve a higher sampling rate?  Looking at the data sheet it looks like both parts are run from the same clock source, which suggests that this is not possible.

I understand that…

HI:

   I have a problem with AD9234-500. When I read by SPI register 0x04,0x05, I receive value 0x00. But in this documentation    have written that chip ID must be 0xCE,0x00. Does it mean that I use bad chip and it will not normally work further.

Thanks…

Hello,

I'm working on a project which uses AD9234. I'm using Kintex 7 FPGA board to receive ADC data. My ADC output data is always 0. I've tried all ADC test modes. Is there any SPI register available to make sure data is available on SERDOUT…

Hi,

We want to use Xilinx VC709 evaluation board that include Virtex7-690T device to connect AD9234 evaluation board.

I saw that Analog Devices is also using the Virtex7-690T device on the ADS7-V1EBZ and connect it to the AD9234 evaluation board…

Hello,

I can't find the reference board schematics for this part (AD9234). I only see the capture board schematics.

Please advise,

Thank you

Ilya

Hi,

I'm using an AD9234 ADC and I'm sampling a dc coupled static signal (low noise). I implemented a statistic for all the samples I receive from the adc in one second (mean, noise, minimum sample value, maximum sample value). The mean-value of my signal…

Hi,

In my setup (see picture) I use an AD9234 Eval board and an AD9528 evaluation board as clock. In order to have enough single ended clocks (8 & 5 only) I soldered an secon CLK- connector to my AD9234 board and I am powering the CLK+/- inputs of the…

Hello Experts,

We are trying to establish order of data that is transferred over JESD to an FPGA. We tried two tests:

one with User data and second one with captured analog data. We use predefined user pattern to tell us the order of data transferred…

hi,

  I'm using the ad9234 in test mode. After config 0x570=0x89, the JESD IP Core works very well. but when I set the 0x550=0xF --> ramp out；the gt_rxdata is correct except the gt3_rxdata.

It‘s very strange, please help me T_T.

In the FPGA…

Customer is asking the following question. Please share your experience :

"We are trying to find a reliable way to manage signal Gnd return between a very wide bandwidth T & H and AD9234, through use of Grounded CPWs.  AD9234 has Pwr-S-S-Pwr…