I am looking at worse case timing for a design that I am doing at the moment using the AD0230 ADC. A typical value is provided on the data sheet, Table 4, for the propagation delay from CLK to DCO, tCPD, but no maximum time is given. Is this figure available…
On page 21 of the AD9230 data sheet : http://www.analog.com/static/imported-files/data_sheets/AD9230.pdf
We read about the shunt capacitor used at the data + and - inputs of the AD9230.
All the termination schemes I've read about use a R value…
Hi, I want to use AD9515 as clock driver to AD9230. According to the spec of AD9515, the low level of clock output is 3.3-1.76=1.54V for LVPECL and 1.0V for LVDS. However, AD9230 recognizes clock as low only when the voltage is below 0.8V. I dont understand…
So according to your algorithm, scheme for generation of pn7 function should be such:
Is it correct scheme? It will be compatible with the AD9144?
But even if I will use the eight registers (...) and the proposed algorithm, I still…
I am using the high speed ADC of AD9230 for DPD feedback channel.
The sample rate was 120MSPS， analog input common mode voltage was 1.46V; and Rbias pin was 0.5V; SDR mode, two complement output.
In order to verify the ADC's noise floor,…
I'm attaching the schematic that matches your AD9230 Eval Brd Photo.
For a past project I used an AD9230 evaluation board with the HSC-ADC-EVALC interface board.
Now I'm moving to a 2-channel design and I was thinking to use the AD9655.
Is is possible to use it with the same interface board?
Since I needed external…
Since we would like to average repetetive signals we are interested in the Integrated NonLinearity of the AD9634. Is there a diagram available like for the AD9230?
From the multistage architecture, is it quite repetitive like that of the AD9230 for 2…