• AD9224

    AD9224 datasheet rev.a
    switching specifications - output delay (tod) :
        what is the maximum delay?, or could the delay extend beyond the next clock
    input?

     

    We do not specify a maximum delay. But the delay will not extend beyond the…
  • AD9224(ENOB)

    AD9224数据手册为何没有给出ENOB数据

  • AD9224 Output Delay maximum spec

    Hi All,

    AD9224 data sheet indicates the output delay is 13ns minimum.

    My customer would like to know its maximum value.

    Please let us know it?

    Best Regards,

    Ricky

  • I have a strange situations with AD9224

    I am trying to interface AD9224 40 MSPS ADC to spartan 3 FPGA. I am generating 12.5 Mhz clock with FPGA and giving it to ADC as a sampling clock.
    What I observe that when I am feeding clock to ADC analog signal (which is to be sampled) attached to it gets…

  • why not ENOB in date sheet for AD9224 or AD9225

    why not have  ENOB in date sheet for AD9224 or AD9225

  • AD9224的逻辑输入高电平最低是3.5V?

    当DRVDD使用5V时,手册上写了,AD芯片的数字输入输出是5V的逻辑电平。当DRVDD使用3.3V时,AD芯片的数字输入输出是3.3V的逻辑电平。但是当DRVDD = 3.3 V时,不知道数字输入的高电平是否需要大于3.5V呢?芯片手册上没有写明,如下:当我使用DRVDD=3.3V时,如果我使用3.3V幅值的时钟信号,不知道芯片能不能正常工作呢

  • 问题: 高速adc驱动电路的疑惑 ad9224

    目前在从事一个ccd图像采集系统的项目。项目采用的ccd芯片是柯达的KAI-1020,芯片的输出电路采用自相关双路输出,VoutA,VoutB,这两个的输出电平介绍是在7-11V(手册36页)。我想采用ad9224对其输出信号采样,不知道怎么设计adc的驱动电路。还请大侠指导。或交流,qq408645743.谢谢

  • AD9224加时钟后,为什么在输入端信号出现毛刺

    用AD9224进行模数转换,在不给AD芯片加时钟的条件下,AD输入端的波形是光滑的。可是给AD加12.5MHz的时钟之后,在AD信号输入端的波形会出现毛刺,换别的频率的时钟也同样出现毛刺,不知道什么原因。有没有什么方法可以消除输入端的毛刺呢?

  • AD9224加上12.5MHz的时钟后,在输入端的信号会出现毛刺,不加时钟信号输入端的信号波形是光滑的,这是为什么呢?怎样消除输入端的毛刺呢

    AD9224加上12.5MHz的时钟后,在输入端的信号会出现毛刺,不加时钟信号输入端的信号波形是光滑的,这是为什么呢?怎样消除输入端的毛刺呢

    已经测试过了,确实是AD的时钟给输入端信号带来的噪声,但是不知道怎样消除?

    求指教

  • Differential signal Power divider

    Hi,everyone!

    Recently,I need to use one channel  differential signal which is a output of AD8131 to drive two ADC that is AD9224  in my project.So I want to turn one channel differential signal into two channels differential signal.Is there some chips in ADI…