• AD9224

    AD9224 datasheet rev.a
    switching specifications - output delay (tod) :
        what is the maximum delay?, or could the delay extend beyond the next clock


    We do not specify a maximum delay. But the delay will not extend beyond the…
  • AD9224(ENOB)


  • Differential signal Power divider


    Recently,I need to use one channel  differential signal which is a output of AD8131 to drive two ADC that is AD9224  in my project.So I want to turn one channel differential signal into two channels differential signal.Is there some chips in ADI…

  • RE: AD8138 Evaluation Board

    Hi, Jay.Wang.

    The only difference between the two evaluation boards is the ADI part used wherein AD8138AR-EBZ utilizes AD8138 while AD8138AAR-EBZ utilizes AD8138A. The latter, AD8138A, is neither mentioned on the AD8138 product page nor on the AD8138…

  • why not ENOB in date sheet for AD9224 or AD9225

    why not have  ENOB in date sheet for AD9224 or AD9225

  • After the 12.5MHz clock is added to the ADD9224 clock pin, there is a burr at the input end. Why is this? How to el

    When the AD9224's clock pin is disconnected, the burr of the input port will disappear.

  • RE: The design question of AD8338

    Hi Jino

    Your replies really help me.But I also have a question about the logic voltage about AD8338.Is it 3V or 5V?Can it drive AD9224 directly without any treating in its output voltage.

  • Logic voltage of AD8338

    Hi All

         I some questions about AD8338.What is the logic voltage of AD8338?Is it 3V or 5V? Can it drive the ADCs that mainly adopt 5V logic voltage such as AD9224.Thanks for all reply.

  • AD9224 Output Delay maximum spec

    Hi All,

    AD9224 data sheet indicates the output delay is 13ns minimum.

    My customer would like to know its maximum value.

    Please let us know it?

    Best Regards,


  • I have a strange situations with AD9224

    I am trying to interface AD9224 40 MSPS ADC to spartan 3 FPGA. I am generating 12.5 Mhz clock with FPGA and giving it to ADC as a sampling clock.
    What I observe that when I am feeding clock to ADC analog signal (which is to be sampled) attached to it gets…