Hi,
It is not specifically described in the text of the AD9222 data sheet, but it is described in AN877, which is referenced in the AD9222 data sheet. It would have been better to have it explicitly described in the AD9222 itself, sorry for the inconvenience…
Hi Doug,
I check AD9222 before I check AD9633. And AD9222 datasheet say that SCLK&CSB are both 1.8 V and 3.3V tolerant. For SDIO of AD9222, it say that this pin is only 1.8V tolerant. If applications require this pin to be driven from a 3.3V logic…
Hello all,
I have a PCB board with AD9222 on it.
I replaced it with the faster AD9637- and it is working .
I noticed that pins 13 and 36 on the AD9637 are marked DNC, but on AD9222 they are connected to ground.
Can some tell me it is OK to leave this…
Hi Mr. Metelko,
Thank you for your interest in AD9222. FYI, here is some information about someone who replaced their AD9222 with the newer AD9637. They are almost pin-compatible, with the differences as noted in the thread.
https://ez.analog.com/message…
How many times can I use the power-down mode? Can I apply this mode periodically?
The AD9222 Eval Brd requires the "HSC-ADC-FIFO5-INTZ" adaptor brd to interface to the HSC-ADC-EVALCZ as noted on our High-Speed ADC Evaluation Brd Info portal at: http://www.analog.com/en/analog-to-digital-converters/ad-converters/products…
I'm using an AD9222, and my goal is to program each on-chip ADC in order to test my connection between the AD9222 and my FPGA. So for each ADC I've to set the "Output Test Mode" register.
I read in the AN877 that : During a write…
Indeed, the output register of the SERDES is max. 10 bits wide, but it should be possible to get the data in chunks - for example for a 12 bit ADC get the data in 2 chunks of 6 bits.
This document - http://www.altera.com/literature/ug/ug_altlvds.pd…