Dear Team,
The AD9213 is a Complex ADC or Real ADC. Since by default it uses single converter (M = 1) and 16 lanes.
Thanks in Advance
Goli Ganesh
Dear Team,
The AD9213 is a Complex ADC or Real ADC. Since by default it uses single converter (M = 1) and 16 lanes.
Thanks in Advance
Goli Ganesh
Hii Dougl,
Could you please share me the FPGA source code for AD9213 ?
Hi experts,
I have a EVAL-9213 board to do some test. Some test modes in 9213 were not worked very well.
For exmple, i want send user data from register 0x558 to 0x55f, but 9213 can't work.
Some registers configurations were as below:
0x0000 --> 0x81…
Dear Community members,
We are going to use AD9123 with Xilinx FPGA.
The ADC sampling clock frequency is 8GHz.
The following are link configuration parameters
LR=10Gbps, L=12, M=1, F=1, S=8, HD=1, N=12, N'=12, CS=0, K=32
In this case samples will be…
Hi, it's not clear whether you found the answer to your question. This hi-tech global board block diagram is incomplete. There is another clock gen IC on the board, the adf4371. So, the HMC7044 generates the ref clocks for FPGA JESD204B tranceivers, the…
Dear Team ,
I am trying to bring up AD9213 on hitech global card ( http://www.hitechglobal.com/FMCModules/12-bitADC_10Gsps.htm) along with VCU118.
As a start I am developing the FPGA design and I am observing AD9208 dual_ebz VCU118 reference design as…
Hello,
Our customer wants to have the graph of analog input bandwidth of AD9213 or the S-parameter data.
Do you have the graph or S-parameter data?
In Sep 2018, the input bandwidth graph was not prepared at that time.
ez.analog.com/.../302401
If it had been…
Hello,
is there any IBIS Model for the AD9213 available?
Or can someone give me a hint where to get the model?
Thanks in advance and best wishes
Matthias