• AD9213 API's

    Hii team,

             Is there any API's for AD9213 ADC. We are using AD9213 with VCU118, since we could not find any  no_os files for AD9213. Is there any software reference for AD9213 ADC.

    Thanks in Advance

    Goli Ganesh

  • unexpected data for the first 16 samples of AD9213

    Hi,

    I'm attempting to test the AD9213 with different test modes. The AD9213 is on the HTG board (part number: HTG-FMC-12ADC-16DAC) and connects to the VCU128 FPGA kit through the FMC connector. On FPGA, I used JESD204 IP from Xilinx to communicate…

  • unexpected data for the first 16 samples of AD9213

    Hi,

    I'm attempting to test the AD9213 with different test modes. The AD9213 is on the HTG board (part number: HTG-FMC-12ADC-16DAC) and connects to the VCU128 FPGA kit through the FMC connector. On FPGA, I used JESD204 IP from Xilinx to communicate…

  • RE: AD9213 FPGA Reference Design

    Hi Dougl,

    our university team is starting to develop a project with ad9213. Would it possible to share FPGA source code with me?

    Thank you very much,

    T. Kulhanek

  • AD9213 - SPI stalling CSB & Word Length

    The AD9213 datasheet (Rev. A), Page 73 implies that the Instruction Phase contains data bits to control the word length of the transaction as it states:

    "In addition to word length, the instruction phase determines whether the serial frame is a read…

  • RE: AD9213 Architecture related queries

    Hi,

    The TRIG_x pin is used for hopping to/from different frequency profiles.

    If you do not need to synchronize multiple AD9213s, you do not need to use Averaged SYSREF mode. Averaged SYSREF mode is for Multi-Chip Synchronization.

    Thank you.

    Doug

  • Missing User patterns data in AD9213

    Hi,

    I'm attempting to test the AD9213 with different test modes. The AD9213 is on the HTG board (part number: HTG-FMC-12ADC-16DAC) and connects to the VCU128 FPGA kit through the FMC connector. On FPGA, I used JESD204 IP from Xilinx to communicate…

  • AD9213 using JESD204B Rx ADI IP: Lane Alignment Problem

    Hi,

    I'm using the AD9213 ADC along with the ADI JESD IP. I have been able to successfully configure the part and link the JESD interface - FPGA Rx Link Layer is reporting "DATA" state. Thus has completed CGS and ILA phases. I then write 0x12 to AD9213…

  • AD9213 PLL Unlocked, Link status CGS

    Hi team,


                I am building driver for AD9213 with VCU118. I have taken AD9208 VCU118 reference, I have tried to configure it, but I am facing some issues related to SDK. Since there are no APIs for AD9213, I am configuring the registers of AD9213 provided…

  • RE: AD9213 test mode - loss of link

    Hii  ,

      I'm also using HTG-12ADC-16DAC FMC board with VCU118. In HTG-12ADC (AD9213), HMC7044 does not generate ADC clock, but only generates ADC_SYSREF. The clock for AD9213 is produced by ADF7431, which is initialized by HMC7044. I want to…