• RE: AD9213 FPGA Reference Design

    Hi Asger,

    Thanks for your interest in the AD9213. I've requested that sample FPGA code for capturing AD9213 outputs be sent to you.

    Please keep in mind that this is sample code written specifically for the ADS8-V1EBZ ( ADS8-V1EBZ Evaluation Board …

  • AD9213 : model number of FMC connector which is used in AD9213-10GEBZ


    Our customer is interested in AD9213 and he wants to evaluate with intel FPGA development board(A10-GX, etc).

    But the FMC connector which is used in AD9213-10GEBZ is different from normal FMC connector.

    He is planning to make adaptor to bridge…

  • Time interleaved AD9213


    I design a system with 10GHz input bandwidth and I need a 20GSPS ADC. So can I achieve 20GSPS by time-interleaving 2 ADC9213?

    Is there any limit with AD9213 that makes it impossible to interleave? For example, the limit input bandwidth of ADC9213…

  • RE: AD9213


  • AD9213 IBIS Model


    is there any IBIS Model for the AD9213 available?

    Or can someone give me a hint where to get the model?

    Thanks in advance and best wishes


  • AD9213 MCS Accuracy

    The datasheet describes that the synchronization accuracy of the chip is 1 sampling period .

    Is it ±1 on many chips?

    If so,one chip synchronized within one sampling period before a sampling clock edge, and the other synchronized chip is synchronized…

  • RE: AD9213 MCS in averaged SYSREF mode

    Hi Doug,

    Thanks for the reply.

    What is the use of CALC_TIME_DIFF[31:0] with different values by reading Register 0x1623 to Register 0x1626?

    Can it also help me prove the MCS ? If yes , the bigger the better or the smaller the better?

  • AD9213 TDC in averaged SYSREF mode

    AD9213 MCS lock has been achieved by reading Register 0x151E Bit1 = 1,then the contents of Register 0x1623 through Register 0x1626 will never change.

    1. At this time, the applied SYSREF_x is still there. So I think it will always change.

    2. Since it is…

  • RE: AD9213 Bring Up

    Hi Doug:

    Thanks for your advice, I synchronized FPGA reference (625MHz = 4*156.25MHz) and signal generator (10,000 = 64*156.25MHz) with the same 156.25MHz clock source.

    There is only two error left in CGS Error and ILAS Error. Got no “RXRESETDONE” error…

  • RE: AD9213, enable JESD204b control bits

    Hi THaddadin,

    Thank you for your interest in AD9213. I'll try to find the answer to your question and get back to you in a day or so.