我的输入信号为0-2V，如果采用单端输入，请问怎么连接。

上图是数据手册中推荐的接法，不过其中的输入信号是交流的。

Dear Engineers,

I encountered some issues about AD9212-40, could you please help check them

1、when CLK doesn't connect the common-mode voltage, what is voltage for pin9（clk-） and pin10（clk+）, should it be 1.6V or 1.25V.

2、  how to start the test…

I am using AD9212 with single-ended input configuration.

As depicted in the picture above, which shown the single-ended input configuration.

However, my input arrange is 0~2V.

Could annyone tell me how to interface a 0~2V signal with AD9212.

Thanks…

Good day.

I use AD9212-40 and don't want to configure it by myself, because the default settings suits me. Thus the FPGA, which control pins CSB, SCLK and SDIO connect them to VCC (CSB pin) or GND (SCLK and SDIO pins). I understand correctly, that…

关于AD9212芯片有以下问题，请解答！

1、AD9212的CLK+和CLK-可以直接由FPGA以LVDS信号提供吗（即FPGA输出引脚通过0.1uF电容直接连接到AD9212的CLK+/-引脚）？

2、AD9212 datasheet  Rev.E 中第22页Figure49单端信号输入图中的R、C、CDIFF的值分别是多少？实际应用电路可以按照该图直接连接2V的单端信号吗？

3、DRGND和AGND可以是一个地吗？在画PCB时需要分开模拟地和数字地，然后再单点将这两个地共地？还是没必要分数字地和模拟地…

1、我看datasheet 应该是只要电源地接通了，DCO、FCO应该是5倍clk+-时钟啊，是这样的吗，我理解的对吗？

2、此问题是第二次贴出来，麻烦版主小编不要将帖子删了，谢谢

我想问一下AD9212-40的时候，无信号输出，这种情况对吗？

PS：其中pin9（clk-）pin10（clk+）当不外接触法时钟时，其电平均是1.6v，外接时钟（峰峰值1.8v和0.8v）时，都是以1.6v为中心的时钟

Hi folks,

I'm trying to program the AD9212 chip into standby mode with FPGA.

I tried to look up the note AN-877 and found that very surprisingly,

in the note it said in the instruction phase the last 13 bits  (A12~A0) are for addressing,

but…