• AD9208 verification model


    I am looking for VHDL or Verilog model for the AD9208.

    I am designing ASIC that would interface to multiple ADC chips and need simulation model to make sure interface is working correctly.

    Any recommendations on IP vendor for jesd204B IP that would…

  • AD9208 information request

    Hi there, 

    I'm interested in the AD9208 but need some information to see if it suits my application. I like to look at the phase differences of multiple channel signals coming in at say 100 to 1.1 GHz. Questions are:

    1) Does the ADC have an onboard…

  • AD9208 S-parameter

    How is the AD9208 S-parameters measured?

    What is the reference plane? Are there any components between the pin and the measurement connectors (i.e 10Ohm resistor/0.4pF cap)? What is the physical length from the pins to the measurement connectors? Is the…

  • ad9208 dither option


    I have a question about disabling the on-chip dither in AD9208. We are currently evaluating the AD9208 ADC to see if it meets our requirement of clean output samples. Higher noise level is acceptable as long as the output is free of deterministic…

  • ad9208 input circuit


    i am using the ad9208.c

    in the ad9208 evb, the input circuit of adc is composed with the balun.

    I think the performance of balun transformer is good. but it has much loss of signals.

    So, I wanted to get information for differential amplifier as…

  • AD9208 SYSREF+/-

    Dear Sir/Madam,

    On page 7 of the AD9208 datasheet table 3 is "Differential Input Voltage" 400mV to 1800mV defined as shown below or VID = 400mV to 1800mV?

    Regards Joe

  • AD9208 SYSREF

    Does the SYSREF signal of AD9208 can be Ac Coupling? If so, how to configure it?


          I need to configure ad9208 through FPGA, but I don't see the register configuration order in the manual. Does that mean I can configure registers out of order?

  • AD9208 Startup & Debug


    I am using the AD9208-3000EBZ with the Xilinx VCU108 Dev Board. I am having trouble getting the AD9208 to initialize correctly. When probing the JESD IP signals on the FPGA side, it appears to initialize and come out of reset as expected, then nothing…