• RE: AD9176: ACE could not find AD9176-FMC-EBZ

    Hi y_suzuki, 

    You should be able to use the DAC Software Suite (includes DPG Downloader). But you could also just install ACE with the HS DAC components and SDP drivers (which includes DPG Downloader Lite).

    I have both installed on my machine without a…

  • RE: AD9176 Spurs

    Strongly recommend following the decoupling capacitors placement of the eval board. These decoupling capacitors had been optimized for these digital spurs. Also no need to add extra caps. 

  • AD9176 API


    I am starting to write our firmware for AD9176; however, I noticed the API referenced in the documentation for AD917x-API only supports AD9171/AD9172/AD9173:


  • AD9176 channelizer


    Recently, I started with AD9176 datasheet. I am completely new to this DAC terminologies and sorry for my simple!!! question.

    My question is that what is channelizer? I see following figure in the datasheet.

    I can see same data is routed to three…

  • AD9176 Settling Time

    What is the settling time for the AD9176 after changing the NCO from one frequency to another?

  • AD9176 NSD Performance


    Do you have some measurement result of AD9176 NSD with 12GSPS and 5GHz output?

    Even if there is a similar evaluation result for other equivalent parts (AD917x), it should be helpful for me.


    Taiki Mineno

  • AD9176 Power Sequence

    The AD9176 Rev B datasheet does not appear to clarify a required power sequence for the power rails.  Can you please define this requirement, or point me to a document that states what this might be? 

  • AD9176 Clocking Recommendations


    With the AD9176-FMC-EBZ evaluation board, we are creating a wide-band transmitter, using specifically JESD modes 12, 20, or 21. 

    As the clocking and the jitter associated with it greatly dictates the overall system performance, would the on-board…

  • AD9176 SYNCOUT

    When using AD9176 in both single-link and dual-link mode therefore need two SYNCOUT signals.

    The data sheet mentions possibility of combining two SYNCOUT signals in dual-link mode inside the DAC (register 0x110, bit 6); Will the combined SYNC signals…

  • AD9176 JESD Formatting


    I wanted to confirm how we are packing bits onto the JESD204B bus with the AD9176.

    We are in Mode 4. We have a complex waveform we are sending to the DAC from our FPGA board. Currently we have lanes 0 - 3. In the table on page 34 the following…