• RE: AD9174- CLKIN Pin Details- Reg

    Hi landsman,

    I need one more clarification regarding this CLK pin connections. Due to placement constraints of my module, I could not connect

    ADF4372-RF16P(26) pin with AD9174-CLKIN+(J12) and

    ADF4372-RF16N(27) pin with AD9174-CLKIN-(H12)

    This connection…

  • RE: AD9174- RF Output Channel Impedance matching

    Hi Sakthi, 

    We do not have an application note on this just yet, but we are certainly considering one. 

    To answer your question: The only difference between a 1:1 and a 2:1 is the impedance ratio. Either can be used. 

    Our data and simulation from the AD917x…

  • RE: ACE Capture View with AD9680, AD9234 and AD9174

    please follow the instructions on the wiki user guide to evaluate the AD9680 and AD9234. These devices are not supported in ACE

  • RE: Error testing high bandwidth modes of ad9174-ebz

    Hi morganh,

    Yes, this is partially true - the DAC rate (Fdac) that must be int-mult of 122.88.   

    The board uses a 122.88MHz XTAL to lock HMC7044 to an external reference. The HMC7044 then generates the FPGA ref clock (=lanerate/40), SYSREF, and the AD917x…

  • RE: AD9174 Start up sequence for NCO only mode

    Hi shafna, 

    Thank you for your interest. Please see attached:



  • AD9174 Frequency Hop


    I need every frequency to hop with 0 phase for my application. How can I make the DAC to Frequency hop at exactly 0 phase. When Ever the frequency hops, the start of the frequency hop should be at 0 phase. Is there an option to set the phase to be…

  • ad9174

    Hi Sir,

    I am using AD9174 with ads8 carrier card. I need to provide the 400MHz Bandwidth chirp as an input. how can i input this kind of data using ADS8

  • AD9174

    Could you recommend an amplifier for AD9174 output ,and the amplifier need to meet 3G bandwidth scenarios, in addition, how to match them? is there need some special circuit matching method?

  • AD9174 initialization question

    When I initialize the AD9174 by API, I find a problem: the AD917x_reset function call the dac_init_sequence function, when reg 0x91 is wrote 0x00, the SPI mode is switched from 4-wire to 3-wire and reg 0x91 is still 0x01(default value). why?

  • ad9174 fmc-ebz ref design with zcu102

    I am working with the ad9174 fmc-ebz eval board on an zcu102 using hpc0 fmc slot. This is what I have done so far:

    1. Followed build instructions at https://wiki.analog.com/resources/fpga/docs/build to run make in projects/daq2/zcu102. This has generated…