I am using ad9174 with jesd link ,I am using dual link with L=4,m=2,f=1,s=1.so I want know that how to arrange I,Q data samples as transport layer data?
In data sheet ,they have given like m0s0,m1s0 like this, its confusing.
On page no. 106 of AD9174 datasheet (Rev. B) there are some DDSM_FTW_REQ_MODE settings (Bits [6:4]) of register 0x113. I have few doubts regarding this setting--
1) If we are selecting any mode other than 000, does that mean we don't require to…
Hi ADI Team,
I am using DAC AD9174 for generating output frequency upto 6GHz with following JESD204B Mode.
Lanes per link: 4
Channels per DAC : 2
Channel Interpolation : 4x
Datapath Interpolation : 8x
I'm studying how to use the AD9174.
Please tell me some about JESD204B mode and datasheet.(sorry for the rudimentary question.)
1.In the start-up sequence (Table.55) of the data sheet, among the setting values related to JESD204B, there was…
I have a similar question about AD9175 and AD9176. I can,t find differences.
Our requirement is that we need two DAC outputs(DAC0 and DAC1), both generating different frequencies, to hop from one frequency to another simultaneously in phase discontinuous mode as described in FFH mode.
I am using AD9174 in my design. I need the following details of CLKIN+/- pin for selecting PLL.
1. Differential input Voltage VIDIFF minimum and maximum,
2. Common mode input Voltage VICM minimum and maximum
3. Allowable Voltage level (LVDS…
I am using ad9174 with nco only with bypassing pll and feeding external clock to the dac!
in this case ,do we need to check pll lock status and dll calibaration status?
what is register configuration for this?
DO NOT use the pdf instructions which come with the CD. Best to ignore the CD.
Use the online "wiki" version. Restart PC after install. If you follow the instructions carefully, it should work. summary below.
1. Run DPG Downloader (load vector…