• ad9173

    您好,我在fpga中采用spi通信读ad9173寄存器时,发现ad9173没有响应。其中spi通信速率为10M完全满足datasheet不大于80M的要求。其中通信方式采用四线制。读取寄存器为0x000. ila抓取的信号如图所示:

    spi通信只控制了spi通信的四根线。ss_n为片选、miso 从机(ad9173)输出主机(fpga)输入、mosi主机(fpga)输出从机(ad9173)输入、sclk0串行时钟线。


  • RE: AD9173 NCO reset

    Please check this information from the AD9174 data sheet.It applies equally to the AD9173.

  • AD9173 DAC TPL core input format


    I removed DMA+FIFO and want to feed both DACs with IQ data from my own DSP core. With original DDS it looks good, but not with my DSP. Datawidth 256bit and rate 250MHz matches together.

    What do I need to configure and how do I need to map the 256bits…

  • RE: AD9173 NCO ONLY mode not working with DAC1

    Facing the same issue, able to get DAC 0  output but For DAC 1 ,not getting any output .please advice the register sequence.

  • Modification on FMCDAQ2 AD9680 & AD9173


    we have designed a board with a zynq ultrascale xczu4cg-fbvb900-1-e, 1x AD9173 12GHz dual DAC, 4x AD9680 500MHz dual ADC and a LTC6952 clock distribution. The DAC I have successfully tested based on the dac_fmc_ebz project, see here. Now as a further…

  • RE: No output for AD9173 NCO ONLY mode

    Try to trigger a rising edge for TXEN

  • AD9173 Deterministic Latency Requirements

    The design need 2 chip AD9173s(4 channel output) with  Deterministic Latency and the AD9173 config parameters as follow:

    Data Rate:3.2G







    Lane Rate: 12G

    I use HMC7044 for clock generator, output clock system as follow:

    The CLK…

  • RE: Questions about debugging methods of AD9173

    Assumed answered offline.  Let us know if you need further assistance on this and we can re-open the case.

  • RE: Problems on using AD9173 NCO ONLY mode

    hai  ,

    Can you please share the answer with me ,I too had same problem.

    I have raised a question also, Please go through it once.

     No output for AD9173 NCO ONLY mode 

    Thank you.