• AD9172 Computed checksum did not match received checksum

    Hi,

    I'm using a VCU128 FPGA board to push data to a DAC9172 on the HTG board (part number: HTG-FMC-12ADC-16DAC). On FPGA, I use JESD204 IPs from Analog Devices to communicate with AD9172 through multiple gigabit lanes.

    Here are my link parameters:

  • AD9172

    hi,

    I'm studying how to use the AD9172.

    Please tell me some questions. (sorry for the rudimentary question.)

    1. I don't understand what M(JESD204B param,the converter count (M) ) means? What is the relationship with DAC.

    2. I want use JESD mode…

  • AD9172 DAC channel delay

    Dear ADI colleagues,

    We have one AD9172-fmz-ebz and ADS8-V1, and working with two channels (mode 19). The AD9172 has an external reference clock input of 122.88 MHz, and is synchronized and frame triggered by an arbitrary function generator. The AD9172…

  • AD9172 DAC Output Issues

    Hii team,

       I'm using the dac_fmc_ebz VCU118 reference design. I'm using AD9172 at 6GSPS DAC rate for this I changed  the JESD parameters based on Mode 20. When I'm programming through SDK the below UART prints are observed for VCU118_AD9172. All…

  • AD9172 operating at full rate with ADS8-V1

    Hi,

    We have one AD9172-fmz-ebz and ADS8-V1. We would like to use JESD mode 20/21 or 18/19 and operate at full rate. 

    With JESD mode 20/21, we can operate at 4.9152GHz DAC rate and the corresponding lane rate is 12.88Gbps. However, we want to further push…

  • RE: AD9172 Test modes Failed

    Looks like the link is not getting through CGS, which measn  there is a clocking issue (incorrect or mismatched reference frequencies between FPGA and DAC?).  See the JESD204B Debug Guide for more details.

  • RE: AD9172 sometimes cannot output however the link is correct

    Assumed answered ofline. Please let us know if there are further questions.

  • AD9172 no-os build fail - undeclared items (Linux) and make error (Windows)

    Hello,

    I am trying to build the no-os project for the AD9172. The starting HDL design I am using is the analogdevicesinc/hdl/projects/dac_fmc_ebz project configured for AD9172, mode 0.

    I followed the instructions at the NO-OS Project Build Guide (https…

  • RE: AD9172 unused output

    Is the same true for the AD9177 unused outputs?

  • RE: AD9172 not generating output data

    Hello,

    For posterity's sake and future readers - the sequence in the current (revA) of the datasheet is missing a short delay before the write to 0x90. This is to allow the bootloader to complete. 

    1mS delay is plenty. Would make sense to do the same…