Hi,

while testing ad9172 jesd with kintex ultrascale, link established properly but cgs,ilas status are not updated in ad9172! I tried to read back the registers related to those status.

what could be the issue? for enabling the two links ,what is the…

Hi,

I am testing AD9172 JESD with FPGA .In DAC ,I am using JMode=8 dual link.as per datasheet , main interpolation is 8 ,channel interpolation is x1 (which means channel datapaths are bypassed).

how jesd data will come through that channel data paths…

Hi

I have used main nco to generate the frequency of 3.84 G and given chirp iq samples through jesd link. but the chirp waveform band width was not as expected .

What could be the issue?

Thanks

VK19

We're trying to bring up an AD9172 on a custom PCB.

We get through PLL and DLL lock. Using ADI IP on the FPGA and ADI linux drivers, the jesd_status tool reports the clocks OK, but the DAC never leaves the CGS state.

On the FPGA, we have looked at…

Hi,

I would like to know how to do the data re-arrangement of the Transmitter transport layer in AD9172.In data sheet ,

Its like M0S0 ,M0S1 its confusing .The JESD Configuration is L=4,M=2,F=1,S=1.J mode of dual link 8.

Here I have to arrange I,Q samples…

Hi,

I'm trying to use AD9172-FMC-EBZ in NCO-only mode. I bring up the JESD link and then configure the data chain to use the main 48-bit NCO only, using the ADI no-OS API. It seems to work, but the DAC output signal level is only about -73 dBm, when…

Hello everyone,
I am working with the HTG-FMC-14ADC-16DAC mezzanine board and now I am trying to configure the ad9172 DAC.
Faced with the problem that I am not getting a sine wave output, maybe you can tell me where I am making a mistake.
I want to use NCO…

Hi,

We plan to use AD9172 to drive HMC8193 I/Q mixer. The final signal frequency is in range of 4 to 8 GHz. The BW needed is 1.5 GHz. The data rate we planned to use was 2.5 Gsps. No interpolation was planned. So, simply I samples on DAC0 and Q samples…

Hi,

I'm using a VCU128 FPGA board to push data to a DAC9172 on the HTG board (part number: HTG-FMC-12ADC-16DAC). On FPGA, I use JESD204 IPs from Analog Devices to communicate with AD9172 through multiple gigabit lanes. The DAC9172 was configured to…

I use Xilinx's FPGA to connect to ad9172.

The input data of my DAC is DDS, jesd can be synchronized, and DA can work normally.

However, the data after DDR cache collected and processed by ad can not be synchronized with the jesd of DA.

This part of…