• AD9172 linux driver / device tree question

    Someone ask by email:


    With the AD9174, in wideband mode using the JESD mode 10, it is allowed to set the DAC main path interpolation to x2 or x4 which we need for a new project. This will allow us with the same input data rate to run the DAC at…

  • RE: AD9172 JEDS204B interface mapping?


    can you share a photo of the spectrum? 

    The DAC uses unsigned data.



  • RE: AD9172 CHECKSUM IS 0, LID2=0x1C, which is Complement of 0x3

    I have solved the problem by reverse polarity of lane0 and lane3. but I check the schematic, and find the original schematic reverse all low four lane(lane0-lane3), why I just reverse lane0 and lane3 can solve the proble?

    the original schematic is zcu102…

  • RE: AD9172 Dual Channel Example Spectrum Noisy Problem

    Dear ADI experts,

    We have two ADS8-V1EBZ's, and AD9172/AD9213.

    So I tried connected two different ADS8-V1EBZ board to AD9172.
    The results are the same, when I set the power of multi-tone vectors(dual channel) to -10dB, DAC output becomes noisy.
    In different…

  • AD9172 CHNL_GAIN

    Is it possible to control the ad9172 CHNL_GAIN from the Linux drivers ?

    If so, how ?

    below is list of the drivers directory on our Linux :

    root@vhs-500-621:~# ls -ltr /sys/bus/iio/devices/iio:device2/
    total 0
    -rw-r--r-- 1 root root 4096 Jan 1 1970 ueve…

  • RE: DAC AD9172 Mode selection & Register configuration

    Hello, sorry for the delayed response.

    Following the sequence in tables 49-58 of the rev B data sheet is the appropriate method for bringing up the device. the serdes PLL being locked is a good sign.  SYCNOUT will be asserted low once the link is enabled…

  • ad9172 Evaluation Board


    I am using AD9172 evaluation board with the capture board. When using high lane rates link occasionaly get lost. Is it something expected? Or is it something about heating?  

  • AD9172 clock support

    1. Can AD9172 be used in the 2nd Nyquist zone i.e, ~6-7GHz?  If yes, please suggest a matching transformer circuit. Driver circuit may also be fine is IMDs at max DAC output < 80dBc.
    2. We are providing AD9172 clock = 642.15 MHz to generate a sampling clock…
  • AD9172 Power

    I'm trying to estimate power consumption in 2 different use cases:

    1. I,Q channels enter DAC at 1.5Gsps each (don't care too much how JESD transport is configured, lowest power preferred), internal interpolation of 2x, output 3Gsps on both channels…