• the minimum dac rate of ad9172

    The Minimum DAC UPDATE RATE of ad9172 is 2.91GSPS in datasheet.What is that mean? The ad9172 can not work below 2.91GSPS?

  • For AD9172 the PLL for CLKIN does what?

    I would like to use the AD9172 in place of AD9162.  I have a few questions after reading the data sheet for AD9172.

    • Are the two DAC isolated?  If DAC 1 is playing a tone, will I see that tone on DAC 2?

    • If we used this part, then we would have to use…
  • RE: AD9172 Example HDL

    Hi Ray,

    I just pushed this branch here:



    It has the device tree for ZCU102.

    This is still work in progress but the JESD links on all lanes come properly up at 14.75Gbps.

    For your convenience…

  • RE: How to Interface FPGA to High Speed DAC using JESD204B interface?

    There are no open designs yet for the AD9172, only prebuilt ones available under links here: AD9171/AD9172/AD9173 Evaluation Board [Analog Devices Wiki] 

    Same question was asked today: AD9172 Example HDL 


  • Input impedance matching of ADL5335


    My customer is designing a wideband transmitter with AD9172 & ADL5335.

    Analog ouput impedance of AD9172 is 'Differential Impedanc 100Ω' in AD9172 datasheet.

    Input impedance of ADL5335 is 'Differential input drive 50Ω' in ADL5335 datasheet…

  • AD9173 HDL reference


    we want integrate the AD9173 12GHz dual DAC into our new SDR board. For the HDL part I have found this thread for the AD9172:


    I have also found this device…

  • RE: AD9172-FMC-EBZ Schematic

    Hello, what browser are you using?  The link seems to be working for me with Chrome and IE.


  • RE: AD9173/AD9172

    The major limitation of AD9172/AD9173 output BW is the package parasitic capacitance and impedance mismatching. the sinx/x filter is only able to help to little bit. so it's not supported by the AD9172/73. 

  • RE: AD9174 Maximum Analog output frequency generation

    Whether AD9174 is pin compatible with AD9172, AD9173, AD9175 and AD9176. Can a common board layout be maintained to support all the chips.



    The sampling rate per data stream is 368 Msps for the default configuration. The HDL needs to be rebuild for other use cases in order to be able have a larger bandwidth.

    The maximum complex datarate for the AD9172 is 1.54GSPS so you won't be able…