• AD9172

    hi,

    I'm studying how to use the AD9172.

    Please tell me some questions. (sorry for the rudimentary question.)

    1. I don't understand what M(JESD204B param,the converter count (M) ) means? What is the relationship with DAC.

    2. I want use JESD mode…

  • AD9172 unused output

    In our application, we may combine the two DAC cores internal to the DAC, and just use one differential DAC output, say, DAC0.  In this case, we’re wondering what to do the unused DAC1 differential output.  Should we just ground both pins, or leave…

  • AD9172 Test modes Failed

    1. PHY prbs testing failed:

                         For this testing we followed the procedure given in page 47 of the data sheet, but we are reading register 0x31D as 0xFE which means the test is failed ,

    we currently enabled only one lane for this testing and the…

  • AD9172 Mode4 usage Doubts

    Hi 

    Dear team,

                     I am using AD9172 Reference design with mode 4 single link. I am trying to use both the DAC's exclusively .During this process I am facing some issues which I mentioned below

    Output’s when both the DAC’s path NCO’s are enabled…

  • I can NOT download AD9172-FMC-EBZ Board File

    I'm DFAE in Japan.

    My customer asked me to get AD9172-FMC-EBZ Board File.

    There is the link to it in https://wiki.analog.com/resources/eval/dpg/eval-ad9172

    But, I can NOT open it. looks like the lik is broken.

    Would you give me the link to the file…

  • AD9172 Architecture related Queries

    Dear team,

                      I am trying to explore AD9172 and as a start I downloaded the reference design and trying to understand it .Reference design is for mode 4 (channel interpolation => *4,main data path interpolation => *8) .Now my doubts are as follows…

  • RE: AD9172 DAC_PLL not getting locked

    we are in middle of integrating it to ADISimPLL. will post on ADI website once available. strongly recommend to use the filter of AD9172 eval board as the starting point. it had been fully validated at different rates. 

  • AD9172 GOOD_CHECKSUM is always 0

    I use the official routine to transplant to my own development board. The official routine runs normally on zcu102 and the official AD9172-EVM. After the transplant, the output information shows that GOOD_CHECKSUM is 0, but the sync signal is 1, and there…

  • JESD204 IP for AD9213 and AD9172

    Hi,

    I want to use VCU128 FPGA Evaluation Kit for capturing the data from AD9213 and transmitting data to AD9172 (part number: HTG-FMC-12ADC-16DAC) and I have 2 questions:

    1. Do the JESD204 IPs from Analog Device support AD9213 and 9172? (JESD204 interface…

  • AD9172 ZCU102 Issues and clarifications

    Dear team ,

                         I am trying to modify the AD9172_ZCU102 design to microblaze design(usign ZCU102 only).As a first step I used AXI Quad SPI instead of PS SPI and generated bit file .When I tested this bit file AD9172 is not getting initialized .What…