1. I believe the formula is not exact.
Let me give one example.
DACCODE is 2's complementary code:
When DAC code = 32767, the differential current = 32767/32768 x IOUTFS x RINT (RLOAD + RINT)
When DAC code = 0 the differential current = 0/32768 x…
where i can find a hdl reference design for AD9171-fmc-EBZ or equivalent that can work with it
The AD9171 is rated for up to 6Gsps sampling rate and supports up to 500Msps at the DAC input while the AD9172 is rated for 12Gsps and supports up to 1500Msps at the data input.
There are no open designs yet for the AD9172, only prebuilt ones available under links here: AD9171/AD9172/AD9173 Evaluation Board [Analog Devices Wiki]
Same question was asked today: AD9172 Example HDL
AD9171/AD9172/AD9173 Evaluation Board [Analog Devices Wiki]
download the .brd file through link, open in an Allegro PCB viewer. See fab1 layer.
In general, if your physical lane mapping is matched to what the FMC connector expects by default, you shouldn't have to remap. Consider comparing your FPGA FMC mapping on the schematic to the FMC connector on the AD9172 EVB.
You can connect the AD9172 EVB, which is FMC-complient, to either the ADS7 or the ADS8 FPGA evaluation platforms.
However for DDS mode there is no need for an FPGA, and the DC reference to set the NCO output level can be generated on-chip…