• AD9164-FMCC-EBZ with AD9164 Controlled with LabVIEW

    Hello,

    I can control the output of the AD9164 daughter card by using ACE and DPGDownloader.  However, I want to control it in an automated way using LabVIEW, either directly using VIs or indirectly like running a command line argument within LabVIEW. 

  • JP1 in evaluation board of AD9164

    I am using AD9164-FMC-EBZ. Should I remove the jumper on JP1 if using an external 10 MHz reference?

  • AD9164 jesd204b PHY lane data grab

    I want to grab data from ad9164 jesd204b lanes, but I followed the procedure described in reg 0x31e of the table 46 of the ad9164 datasheet,

    but when I read data from 0x31f - 0x323 I got  value of 0.

    this is my c code:

    int phy_data_snapshot(ad9164_handle_t…

  • ad9164 phase continuity when updating FTW of the same NCO

    Hi All,

    We are going to replace ad9162 with ad9164 in our project to prevent phase discontinuity when changing NCO frequency.

    We are thinking about using only the main (48-bit) NCO of ad9164 since we already tested our project with the 48-bit NCO of ad9162…

  • RE: AD9164 NCO Phase Truncation

    Assumption not applicable :-(

  • AD9164 reset the nco

    when I configure the register 0x3F =0xc8 to use tx_enable reset the NCO,what level to reset the nco on the tx_enable pin?  a high pluse(logic1) or  a low(logic 0) pluse ?

  • Phase Noise comparison between AD9164 and AD9174

    I like to compare the phase noise of AD9164 and AD9174.

    Is there an app note that enables to compare the phase noise performance for the same fclk?

    What is the 1/f phase noise of AD9164 and AD9174?

  • AD9164 stuck at CGS

    Hi

    as per title, AD9164 stuck at CGS(0x470 = 0x00). I am suffering this issue which is very similar with this guy:  ad9164 sync never goes high , but unfortunately, no answer for this post...

    design parameter as:  2.5Gsps with 8 lanes,so the LaneRate is 20*2…

  • ad9164偶尔输出不正常

    用FPGA配置AD9164,大部分情况下正常输出,输出功率配置为最大(寄存器0x41 =03, 0x42=ff),但是偶尔会出现以下两种情况

    1、上电或者复位后,输出功率很小,只有-30dbm左右,检查寄存器0x281的锁定状态都正常,FPGA端采集sync信号正常拉高。复位DA配置或者重启后正常

    2、上电或者复位后,没有输出,检查寄存器0x281的锁定状态都正常,FPGA端采集sync信号正常拉高,FPGA的204b接口一直在发K28.5码,复位DA配置或者重启后输出正常。

    以上问题偶尔会出现…

  • RE: how to calculate the checksum of ad9164

    Assumed answered offline. The checksum can be calculated by bit field or by register (see reg map for control bits) and can be read back (also in the reg map)