• AD9163 Strange and inconsistent output behavior


    I have been trying to use the AD9163 DAC with the configuration detailed in its user guide (UG-1526), and so far my results have been very far from what is detailed in this document.

    Following the troubleshooting steps showed no improvement. With…

  • RE: [KC705 + AD9163] Wrong waveform visualization

    Hi everyone, in the end I managed to correctly display the sinusoid, it was a problem of how to sort the octets to the Xilinx Jesd IP.

    However, despite the fpga and the ad9163 can reach the jesd connection, the syncout and data ready are high, sometimes…

  • AD9163,ADS8 issue

    I am at a customer, we're trying to run the AD9163 with ADS8. Everything is talking, but we can't get JESD to indicate sync and JESD lane rate is indicating something like 4.1gbps when the conditions we have set should put lane rate well under 1gbps.…

  • RE: AD9163 IRQ LED

    ACE works with ADI's ADSx evaluation platforms. If using KC705, you can use libiio and ADI's JESD204 Framework IP.  Follow this thread for more information.

  • RE: AD9163 JESD problem

    If SYNC is held low, then CGS phase is not completing.  Most likely a clock issue such as wrong frequency on one end of the link or the other see the JESD204B Debug Guide for more tips.

  • AD9163 register config

    I am trying to setup the AD9163 board. I made a following setting sequence refering to start up sequence. And add the CDR reset of updated start-up sequence.
    but didn't go well.
    I tried to check address 0x31E PHY_DATA_SNAPSHOT function,but the snapped…

  • ad9163-fmcc-ebz high output noise

    If i connect the ad9163-fmcc-ebz DAC output SMA to oscilloscope ,once the FPGA (I've tried Xilinx board KC705,VC709,KCU105 with official power adapter) power is on, there is a hugh output noise.

    The noise is still on when the jesd204b link is established…

  • RE: AD9163 Sync sygnal low


    If I understand correct, you are using 100 MHz reference to ADF4355 and your VCO frequency is 4800 MHz. If your PFD frequency is 100 MHz you should follow a special programming sequence as given in Page 29. Not sure if the root cause of your problem…

  • AD9163 SYNCB deassert after device reset

    The AD9163 on my board does not deassert SYNCB after the start up configuration.

    The SYNCB always deassert keep HIGH with some negtive pulse after DAC reset.

    Is this SYNCB normal?  

  • AD9163 parameter in datasheet no difinition

    Hello, I can't understand the relation between "Fclk", "Fout", "Fdac", "DAC rate", "DAC clock", "Clock input"  in AD9163 datasheet.

    Is there any definition avaliable for those words ?