• RE: AD9163 Sync sygnal low


    If I understand correct, you are using 100 MHz reference to ADF4355 and your VCO frequency is 4800 MHz. If your PFD frequency is 100 MHz you should follow a special programming sequence as given in Page 29. Not sure if the root cause of your problem…

  • AD9163 register config

    I am trying to setup the AD9163 board. I made a following setting sequence refering to start up sequence. And add the CDR reset of updated start-up sequence.
    but didn't go well.
    I tried to check address 0x31E PHY_DATA_SNAPSHOT function,but the snapped…

  • AD9163 SYNCB deassert after device reset

    The AD9163 on my board does not deassert SYNCB after the start up configuration.

    The SYNCB always deassert keep HIGH with some negtive pulse after DAC reset.

    Is this SYNCB normal?  

  • AD9163 parameter in datasheet no difinition

    Hello, I can't understand the relation between "Fclk", "Fout", "Fdac", "DAC rate", "DAC clock", "Clock input"  in AD9163 datasheet.

    Is there any definition avaliable for those words ?


  • AD9163 SERDES PLL locked, but DLL unlocked

    Hello, I am debugging on AD9163 of the custom board.

    The DAC device clock is 4.8G and jesd204b is 8 lane with 4G lane rate.

    Other configration was as followed:

    0x110=0x84    // 8lane and 6 interpolar

    0x230=0x0     //lane rate less than 6G

    0x289=0x01   //ref…

  • AD9163 both lane fifo full and empty are asserted

    hello, I am debuging the AD9163 on my board. Now the syncout was never get high. And both lane_fifo_full(REG 0x30C) and lane_fifo_empty(REG 0x30D) are get HIGH.

    Can somebody give me a help?

  • The thickness of the AD9163 package


    I have a question from our customer about the thickness of the AD9163 package.
    The maximum height from the bottom of the ball to the top of the package is 0.95mm which is described in the figure-141 of the datasheet.
    This customer wants to know whether…

  • RE: A10SoC+AD9163-FMCC-EBZ Boot/linux problem

    You don't need to compile u-boot from scratch. Regarding the image please use the latest image form here:


  • AD9163 datasheet can't understand

    Datasheet of AD9163, Rev.d, page 67, the explanation of 0x604 bit 1 is shown as followed:

    (Optional) read the boot loader pass bit in Register 0x604, Bit 1 = 0b1 to indicate a successful boot load (private).

    What's the meaning of 0b1 ?

  • AD9163 DLL can't lock

    I am using AD9163. The dac clock is 400Mhz. I used an oscilloscope to observe the 400MHz dac clock is right.

    But the context of REG 0x092 bit0=0, which means DLL is not locked.

    What can I do next to figure out this issue?