• AD9162 CLK INPUT

    The AD9162's CLK INPUT (datasheet p78) is described as being able to be connected to a single-ended clock source.

    What is the circuit configuration for connecting to a single-ended clock source?

    Is it possible to input a single signal directly to…

  • AD9162 : minimum reset pulse width for AD9162

    Hello,

    I got an answer to my previous question.

    https://ez.analog.com/data_converters/high-speed_dacs/f/q-a/102024/ad9162-changing-clk-frequency

    This answer recommended to be reset after changing the clock frequency.

    And I gotten a new question from our…

  • AD9162 : ACE can not operate AD9162-FMCC-EBZ

    Hello,

    I have a trouble of ACE when connected to AD9162-FMCC-EBZ.
    The ACE find the AD9162-FMCC-EBZ as AD9162-ADF4355-FMCC-EBZ.
    But ACE can not connect to this evaluation board.
    ACE version is "1.17.2873.1284" and AD9162 plug-in is "1.2019.20300",…

  • AD9162-FMCC-EBZ : SYSREF does not reach to AD9162

    Hello,

    Now I'm cheking phase relation between SYSREF and DAC Clock on AD9162-FMCC-EBZ by request from our customer.
    (Subclass 1 use)
    I captured SPI waveforms for control AD9508 because I could not check register data from ACE.
    Followings are decoded…

  • AD9162 - What is the expected value of chip_type (register 0x003) of AD9162?

    I'm trying to determine if my VHDL is correctly reading register data from the connected AD9162.  I figured I can read back the CHIP_TYPE (and perhaps Product ID) as a measure to see if the readback is working right.  However, the datasheet does not…

  • AD9162-What is the Noise spectral density in dBFS/Hz for the AD9162?

    For 40mA output and assuming 50ohm termination, the max output power is 10dBm for a sine wave. The NSD is specified as -165dBm/Hz which implies a noise floor of -175dBFS/Hz. Is that conversion correct? What is the dominant noise source in this DAC?

  • RE: AD9162 does not achieve CGS anymore

    Just a couple of comments.  The SYNCOUT is always low during the CGS phase on the channel that is failing.  Regarding the clock, I am running at 2GHz.  I use a common clock to drive 8 DACs on a single board.  The clock is distributed as LVPECL using a ADCLK954BCPZ…

  • AD9162 output issue

    DEARS.

    If we set the NCO frequency to 1.2GHz and send data from the FPGA, the following waveform is output.
    The result we want is a single tone pulse at the 1.25 GHz point.
    Changing the JESD204B data has a pulse at the desired point.
    However, it produces…

  • AD9162

    Dear Sir/Madam,

    For the  AD9162 SPI register configuration, do I only need configure the sequence register, without  configuring other register.  is there command for reading the sequence  register.

    Thanks.

  • RE: AD9162-FMCC-EBZ : the effectiveness of the isolation of the output section

    these two inductors are optional if SA(spectrum analyzer) or similar GND is not noisy.