• I/Q modulation by AD9162-FMC-EBZ EVB

    Hi

    As simple question about AD9162, is it possible to implement I/Q modulation by AD9162-FMC-EBZ EVB connecting to an ADS7-V2 ?

    Regards,

    Hiroyuki

  • AD9162

    Dear Sir/Madam,

    For the  AD9162 SPI register configuration, do I only need configure the sequence register, without  configuring other register.  is there command for reading the sequence  register.

    Thanks.

  • RE: AD9162 s-parameter and IBIS AMI model

    There is no specific IBIS-AMI model for the AD9162 DAC. We are aware of the package differences between AD9144 and AD9162 but still suggest that customers use the IBIS-AMI models for the AD9144 since the JESD core and PHY are the same design. The package…

  • Differences between AD916x

    Hi All,

    I already know that the minimum interpolation setting is different between AD9162/4(1x) and AD9163(6x).

    Is there any difference between AD9162/4 and AD9163 except the minimum interpolation value ?

    Additionally, please explain the differences between…

  • IS there matlab API for ad9162?

    I would like to use the ad9162 DAC as a signal generator. I have the ad9162-fmcb-ebz and the ads7-v2ebz. Instead of using the ACE GUI, I would prefer to use only Matlab. I know I can run the ads7-v2ebz using only Matlab however the ad9162 still requires…

  • AD9162 : Changing CLK frequency

    Hello ,

    I have a question from our customer about changing clock frequency for AD9162 CLK input.

    He use AD9162 as NCO only mode. (He does not use SERDES data inputs)

    He said, he will change the ferquency of CLK while the AD9162 is running.

    And he asks…

  • Why is my AD9162 Eval Board not Locking to an external reference clock?

    I am trying to control an AD9162-FMCB-EBZ evaluation board using a Xilinx KCU105 evaluation board and an external reference clock.  I have written firmware to control the ADF4355, AD9508, and AD9162 on the evaluation board, but I cannot seem to get the…

  • AD9162 ILAS errors

    I have a AD9162-FMC122-EBZ eval board attached to a Xilinx ZCU102 Ultrascale+ eval board.   I created a JESD204B transmitter based on the Xilinx JESD204 sample design.  The transmitter and AD9162 are operating in Subclass 0 mode, so SYSREF is not used.

  • AD9162 : minimum reset pulse width for AD9162

    Hello,

    I got an answer to my previous question.

    https://ez.analog.com/data_converters/high-speed_dacs/f/q-a/102024/ad9162-changing-clk-frequency

    This answer recommended to be reset after changing the clock frequency.

    And I gotten a new question from our…

  • AD9162 IBIS-AMI

    For the AD9162 IBIS-AMI, please refer to the AD9144 IBIS-AMI model. Note that the performance for this model will be a "worst case" since the AD9144 is a bonded LFCSP (QFN style) and the AD9162 is a die mounted flip-chip BGA, which has better performance…