Would anyone please tell me if the schematics for AD9162/9164 downloaded from the https://wiki.analog.com/resources/eval/dpg/eval-ad9162 reliable?
The schematics I downloaded show the chip as AD9162XBCZ, and the pins connection is not consistent with the…
When AD9162-FMCB-EBZ: DAC Eval board is connected to ADS7-V2EBZ board via FMC connector, PWR_BAD LED is lit (according to https://wiki.analog.com/resources/eval/dpg/ad916x-fmcx-ebz it means that AD9162 is not powered properly, however 12v power…
For the AD9162 SPI register configuration, do I only need configure the sequence register, without configuring other register. is there command for reading the sequence register.
There is no specific IBIS-AMI model for the AD9162 DAC. We are aware of the package differences between AD9144 and AD9162 but still suggest that customers use the IBIS-AMI models for the AD9144 since the JESD core and PHY are the same design. The package…
I already know that the minimum interpolation setting is different between AD9162/4(1x) and AD9163(6x).
Is there any difference between AD9162/4 and AD9163 except the minimum interpolation value ?
Additionally, please explain the differences between…
I would like to use the ad9162 DAC as a signal generator. I have the ad9162-fmcb-ebz and the ads7-v2ebz. Instead of using the ACE GUI, I would prefer to use only Matlab. I know I can run the ads7-v2ebz using only Matlab however the ad9162 still requires…
As simple question about AD9162, is it possible to implement I/Q modulation by AD9162-FMC-EBZ EVB connecting to an ADS7-V2 ?
I have a question from our customer about changing clock frequency for AD9162 CLK input.
He use AD9162 as NCO only mode. (He does not use SERDES data inputs)
He said, he will change the ferquency of CLK while the AD9162 is running.
And he asks…
I am trying to control an AD9162-FMCB-EBZ evaluation board using a Xilinx KCU105 evaluation board and an external reference clock. I have written firmware to control the ADF4355, AD9508, and AD9162 on the evaluation board, but I cannot seem to get the…
I have a AD9162-FMC122-EBZ eval board attached to a Xilinx ZCU102 Ultrascale+ eval board. I created a JESD204B transmitter based on the Xilinx JESD204 sample design. The transmitter and AD9162 are operating in Subclass 0 mode, so SYSREF is not used.