• AD9162-Syncout Signal voltage levels

    Hi Team,

      We are using AD9162 in our design we are facing issue wrt to syncout signal toggling.

    Note:Syncout P and N terminated with 100 Ohm resistor

    We are getting below voltage when we probe with multimeter wrt to Ground

    SYNCOUTP- 0.216V

    SYNCOUTN-0…

  • AD9162 Differential output to single ended without a balun

    I would like to generate  baseband (DC to 100Mhz) out of out of the AD9162 DAC However there are no transformers that go to DC.

    And if I find one close they are huge.

    Can the AD9162 output be run as a single ended output? Or is there an op-amp that would…

  • AD9162: Calculation of LMFCDel with known delays

    Hello,

    I have a question about AD9162 calculated expression for LMFC Delay.
    In the calculation which is described in section 7 of page 56 of the Rev.D  datasheet described as follows.

    7.  Calculate LMFCDel as follows:
        LMFCDel = (MinDelay − 1) % (K/PClockFactor…

  • Triggering EVAL-AD9162 and ADS7-V2EBZ

    I have successfully set up the AD9162 and ADS7 to be used together and appropriately output a desired waveform based on a.csv file input to DPGDownloader.

    I still have a prevailing question of whether an external trigger may be supplied such that the…

  • RE: AD9162 - Configuration

    So sorry for the delay and for the inconvenience.  I guess you are using the remote evaluation tool?  If so, due to COVID, personnel are unavailable to get into the lab and get the setup back up and running.

  • Generate a single carrier baseband waveform with 2GHz of bandwidth with AD9162

    Hi, I am trying to generate a baseband signal for IEEE 802.11ay standard with 2 bounded channels (3.52 GHz symbol rate) with 2x AD9162 converters and a FPGA baseband processor but I do not know how to configure the converter to make it work.

    In previous…

  • AD9162 CLK INPUT

    The AD9162's CLK INPUT (datasheet p78) is described as being able to be connected to a single-ended clock source.

    What is the circuit configuration for connecting to a single-ended clock source?

    Is it possible to input a single signal directly to…

  • RE: AD9162 output issue

    Assumed this was resolved offline.  If so, please let us know the resolution here.  If not, please post a new EZone query.

  • RE: AD9162 not passing CGS on some devices

    No, this is still an open issue for me.  I find that by maxing out the drive level at the FPGA serdes I can get 7 of the 8 lanes to pass CGS at least some of the time, but I can never get lane 4 to pass.  I am now questioning the device itself.  I am sending…

  • RE: problem to create square wave output with AD9162

    Assumed answered offline. Please submit a new query if you have more issues.