• RE: Some questions about AD9161

    2.1 GHz instantaneous bandwidth is beyond the ability of the AD9161. You could use two AD9161s as an I/Q DAC pair and drive a quadrature modulator with a complex IF modulation.

  • Mix-Mode in AD9161

    Hi all,

    It is mentioned in the AD9161 datasheet that AD9161 can support up to 7.5GHz RF in Mix-Mode,but now the output signal can only access 6GHz in Mix-Mode(0x152 bit[1:0] is 0b01).
    There is too little mention of Mix-Mode in the document, how can I use…

  • Mix-Mode in AD9161

    It is mentioned in the AD9161 datasheet that AD9161 can support up to 7.5GHz RF in Mix-Mode,but now the output signal can only access 6GHz in Mix-Mode(0x152 bit[1:0] is 0b01).
    There is too little mention of Mix-Mode in the document, how can I use it?

  • Is there an FPGA design example available for the AD9163?

    Is there an FPGA design example available for the AD9163 (or AD9161, AD9162, or AD9164)?

  • AD9161 CGS Failure!

    FPGA: XILINX KINTEX-7

    DAC:  AD9161BBCZ (setings: L=1, M=2,  F=4, S=1, JESD lane rate 7.2Gbps)

    Clock: AD9508

    Clock settings:  180MHz  fpga GTX,    2.8125MHz  FPGA  sysref,      2.8125MHz  AD9161

    Descriptions:

    1 Lane JESD204B was used to communicate with AD9161.   KINTEX…

  • AD9161/9162 peak DAC output power

    Hi

     

    AD9161/9162 data sheet on Page 80 mentions "If the AD9161/AD9162 are programmed for an IOUTFS = 40 mA, its ideal peak ac current is 20 mA and its maximum power, delivered to the equivalent load, is 10 × (RINT/(RINT + RLOAD) = 8 mW (that is, P =…

    • AD9161-9162.pdf

  • Basic Setup of AD9161

    Hello 

    I want to use AD9161 and I am very low on FPGA and clock resources, so I want to know if my setup is possible. 

    My REF clock is 3840 MHz. I don't want to use internal PLL due to phase noise degradation.

    I would like to generate a CW signal…

  • AD9161 SYSREF_PHASEx

    HELLO

    I have a question about how to use the AD9161

    It is about the solution when the analog output delay differs when the AD9161 is turned on and off

    I think reading the values ​​of addresses 0x037 and 0x038 and writing that value to 0x037 and 0x038…

  • RE: AD9161 SYSREF_PHASE Register

    Hi,

    In my system fpga xilinx us+ and ad9164 the sysref is distributed by ad9508 such us the evb. I read the 0x37 and 0x38 registers and the value obtained are fc0, fe0 or f80 (after different power on). Are these values goods for subclass 1 sync or there…

  • RE: Supported NP values for AD9161 and AD9135

    For both AD9161 and AD9135 the number of bits per sample is 16 (NP=16). The core DAC truncates the number of bits to 11.