• RE: AD9161

    yes. you can use the same ADS7.  the PWM vector what you described is doable. referring to the datasheet for output power/voltage. 

     

  • RE: I used the DAC_fMC_EBZ and EVAL-AD9161 validation boards in HDL-2019_R2. When I use DDS driver data in DAC_tPL_CORE, AD9161 can give the correct frequency. But when using DMA to transfer data, the frequency is always incorrect.

    The data format you are using is likely incorrect. Before that I would validate the DMA datapath with IIO Scope. 

    If you are using no-os you can enable a TinyIIOd server and you can connect to the board with IIO scope, then you can load a waveform with…

  • AD9161 SYSREF_PHASEx

    HELLO

    I have a question about how to use the AD9161

    It is about the solution when the analog output delay differs when the AD9161 is turned on and off

    I think reading the values ​​of addresses 0x037 and 0x038 and writing that value to 0x037 and 0x038…

  • About AD9161 EVB

    I will use AD9161, so I checked and reviewed AD916x Evm board.

    I have a question.

    In schematic, you use HMC849ALP4CE for sourcing clock to AD9161.

    ADF4355 -> ADCLK914 -> HMC849 -> BALUM -> AD9161

    Why did you connect RFC pin of HMC849 to GND…

  • Mix-Mode in AD9161

    It is mentioned in the AD9161 datasheet that AD9161 can support up to 7.5GHz RF in Mix-Mode,but now the output signal can only access 6GHz in Mix-Mode(0x152 bit[1:0] is 0b01).
    There is too little mention of Mix-Mode in the document, how can I use it?

  • Mix-Mode in AD9161

    Hi all,

    It is mentioned in the AD9161 datasheet that AD9161 can support up to 7.5GHz RF in Mix-Mode,but now the output signal can only access 6GHz in Mix-Mode(0x152 bit[1:0] is 0b01).
    There is too little mention of Mix-Mode in the document, how can I use…

  • Basic Setup of AD9161

    Hello 

    I want to use AD9161 and I am very low on FPGA and clock resources, so I want to know if my setup is possible. 

    My REF clock is 3840 MHz. I don't want to use internal PLL due to phase noise degradation.

    I would like to generate a CW signal…

  • AD9161 CGS Failure!

    FPGA: XILINX KINTEX-7

    DAC:  AD9161BBCZ (setings: L=1, M=2,  F=4, S=1, JESD lane rate 7.2Gbps)

    Clock: AD9508

    Clock settings:  180MHz  fpga GTX,    2.8125MHz  FPGA  sysref,      2.8125MHz  AD9161

    Descriptions:

    1 Lane JESD204B was used to communicate with AD9161.   KINTEX…

  • About AD9161 EVM Kit

    I will use AD9161, so I checked and reviewed AD916x Evm board.

    I have a question.

    In schematic, you use HMC849ALP4CE for sourcing clock to AD9161.

    ADF4355 -> ADCLK914 -> HMC849 -> BALUM -> AD9161

    Why did you connect RFC pin of HMC849 to GND…

  • More Questions About the AD9161

    I would still like the first set of questions I sent to you earlier to be answered but I have encountered a new set of questions I need answered in order to use the AD9161.

    While I was connecting the AD9161 in my schematic and looking at AD916(2,4)…