• AD9154 : how to configure to use AD9154 without DAC PLL ?


    I correct the previous question.

    I have a question about AD9154 from our customer.
    He wish to drive the DAC core from external DAC Clock directly.
    (disable DAC PLL)
    So I would like to confirm the configuration when using without DAC PLL.

    I think it…

  • RE: About AD9154 configuration.

    Assumed answered offline. Please re-submit if not the case.

  • AD9154 ADI公司提供AD9154的C语言API函数吗?



  • RE: some question about AD9154 and AD9142A

    Assumed answered offline. Please re-submit if not the case.

  • AD9154 DAC + PHY PRBS Testing

    I am using a AD9154 DAC and I am trying to use PHY PRBS Testing as described in the datasheet. The DAC PLL is locked but no valid PRBS sequence is fed to the DAC inputs.

    Every time when I finish the test by writing 0 to PHY_TEST_START the PHY_PRBS_TEST_STATUS…

  • RE: ads7-v2er and ad9154-fmc brd quickstart.

    Assumed answered offline. Please re-submit if not the case.

  • ad9154




  • AD9154 work configuration

    Can you give the FPGA code of AD9154 concerning the JESD204B IP configuration and AD9154 register configuration? I can't get the AD9154 working properly at the moment. thank you

  • RE: AD9154 : about RF CLOCK DIVIDER

    Hi y-Suzuki,

    Yes, good point. I corrected this. "FIN" is the "input frequency into J1"




  • AD9154 JESD204 Problems

    Hello, I am working on interfacing an AD9154 FMC card with a Xilinx ZC706 over JESD204 Subclass 1. I have the DAC setup and am able to talk to it over JESD (I have good values on SYNC, FRAMESYNC, and INITIALLANESYNC), however I cannot get a good checksum…