• AD9154-fmc-ebz

    I have downloaded hdl-master from GitHub, but I didn't find the example project for ad9154-fmc-ebz

    best regards

  • AD9154-FMC-EBZ

    I was followed  ACE AD9154-FMC-EBZ Evaluation Board Quick Start Guide .but I don't know what frequence should I connect to J1?

  • AD9154 produces no output after successful JESD link


    I am currently working on controlling the AD9154 DAC from a Xilinx development board and am running into a problem where, sometimes, the JESD link comes up but the DAC does not output any data.

    To make the current design I started with the dac_fmc_ebz…

  • RE: AD9154 Blanking State Machine Blocking DAC Outputs


        are you solve this problem? I have the same problem, look for your help, thank you!

  • AD9694 EVK or +AD9154 EVK_using the FPGA software of ADS7 or ADS8

    using the FPGA software of ADS7 or ADS8  

    Dear team,


    Our customer is going to verify the performance of AD9694 EVB and AD9154 EVB.

    According to the user guide, ADS7 or ADS8 data capture boards are needed.


    But our customer wants to use the only FPGA software…

  • JESD204B Link between ZCU102 & AD9154-FMC-EBZ stuck in CGS


    I am trying to bring up a JESD204B Link between a ZCU102 (TX) and AD9154 on the FMC-EBZ card (RX.) I am using the following parameters: LMFS = 8411, K=32, N=NP=16, subclass 0.

    As a reference for the FPGA design, I took the analogdevices/hdl/projects…

  • AD9154-FMC-EBZ+ADS7-V2-EBZ无法正常链接问题

    Hi ADI:
  • RE: AD9154 SYNC status is low


      pls check the ‘JESD mode’  to see if that is match with you setting in the ACE.  

      BTW,  you can follow the guide as following web page,  to see the case used in the Guide to make sure the kit working by that case .  ACE AD9154-FMC-EBZ Evaluation…

  • AD9154 configure problem


    I use AD9154 in JESD mode 4, LMFS=4211, two links, 2x interpolation, the samplerate is 1536Mhz, fref is 384Mhz. According to EXAMPLE START-UP SEQUENCE , I configure the registers. Now the serdes PLL and dac PLL is locked .I set 0X450 to 0X47D as…

  • RE: AD9154 : how to configure to use AD9154 without DAC PLL ?

    Hello y-suzuki,

    Yes, the PLL can be bypassed. I believe the mux switches automatically to the direct clock path when the DACCLK PLL is powered down. Could you have the customer try 0x1B0=0xFF.