Hello,
I correct the previous question.
I have a question about AD9154 from our customer.
He wish to drive the DAC core from external DAC Clock directly.
(disable DAC PLL)
So I would like to confirm the configuration when using without DAC PLL.
I think it…
Hi ,
You can download the ACE software, add the AD9154 by off shore (without evb bench connected with PC), configure the chip, and save out configuration file by Marco tool.
by the way, you can try the FPGA serdes loop back test first to confirm the…
let me clarify my question clearly. Does the CHECKSUM must be used for AD9154? I used many ADI's converter with JESD204B interface and the checksum for JESD204B protocal betweent the partner always be ignored. JESD204B link can be ok . It is the first…
AD9154寄存器配置是否必须按照规定的步骤进行配置？
是否能提供一个配置表？需求如下:
工作时钟960MHz；8lane；线速率9.6Gbps；不插值，直通模式；NCO=240MHz；开启混频模式；中频信号带宽:670MHz～770MHz。
Can you give the FPGA code of AD9154 concerning the JESD204B IP configuration and AD9154 register configuration? I can't get the AD9154 working properly at the moment. thank you
Hi,
We have a project need to use a lot of AD9154, but this is the first time we use this chip, we purchased the ADS7-V2ER and AD9154-FMC BRD ,then we use the AD9154 SPI PRO software,it gave us a register configuration table, but according to the datasheet…
Hello, I am working on interfacing an AD9154 FMC card with a Xilinx ZC706 over JESD204 Subclass 1. I have the DAC setup and am able to talk to it over JESD (I have good values on SYNC, FRAMESYNC, and INITIALLANESYNC), however I cannot get a good checksum…
你好，购买了一套AD9154和ADS7-V2，参照https://wiki.analog.com/resources/eval/dpg/ad9154-ace-fmc-ebz 配置参数，ACE软件JESD PLL Locked 正常，但是DPGDownloder 中的sync status z状态始终为低，DAC0~3输出端口也无输出信号。请问是什么问题导致出错？期待你们的帮助。
Hi,
I've seen some odd behavior when setting up an AD9154 to operate in SC1 mode, and I was wondering if you could give me some pointers:
- We're operating with a data rate of 600MHz on all four DAC channels, 6GHz line rate (jesd params: l=8,…
