• RE: about ad9152

    But I configure the AD9152 on my board with the mode 7, and the sample clock is 200MHz,then i read the registers,the 0X470-0X473 is really good with a result 0X01,and i read the DAC core is pull up ,and the clock is different and on, the seders PLL is…

  • files AD9152

    Hello,

    I search for the schematic and layout files of the AD9152-FMC-EBZ board. I can not open the links at analog wiki.

    The file is named: "AD9152-FMC-EBZ RevA Schematic.pdf"

    Can you send me a valid link, please.

  • BPSK for AD9152

    Hello ! I am using fpga + DAC AD9151 to generate analog signal. 

    Digital data from my DDS core are sent via JESD204B interface to DAC and i can see analog harmonic signal on an oscilloscope. 

    So i conclude that DDS and DAC is working correctly.

    Next step…

  • About AD9152

    Hi,

          I am using the production of AD9152-FMC-EBZ, now i have a problem about the configuration,the 0x472  is not equal to 0xF。What's wrong?My parameters(such as L,M,F,S and so  on ) are matched with the register values. Also, register 0x604 cannot…

  • AD9152 SYNCOUT

    Hello,

    I have a question regarding the sync output from the AD9152;

    The configuration I am using is:

        AD9152_write_reg(0x0200,0x00); // Power up the interface
        AD9152_write_reg(0x0201,0x00); // Enable power to all lanes    
        AD9152_write_reg(0x0230,0x0A);…

  • AD9152 DC Test mode

    Hello,

    We are trying to get the AD9152 up and running on our own custom boards and are running in to problems trying to configure it in a DC test mode. We are using a 245.76MHz REFCLK. I am setting the registers as in the spreadsheet I have attached…

  • AD9152 Output current

    Hello,

    According to the data sheet on page 75 of AD9154, OUTx +/- are current sinks. But I can't find like that description on page 67 of AD9152. Are output current of AD9152 also current sink? 

    I think the output current of AD9152 is sink current.…

  • AD9152 REFCLK+/- termination

    Hello,

    When REFCLK+/- of AD9152 is unused, what termination is required?

    Best Regards,

  • AD9152-FMC-EBZ

    Due to some logistics issue we fabricated and assembled the DAC eval board(AD9152-FMC-EBZ). Can someone please share the program to be loaded on to the PIC18f24j50  microcontroller which is present on the eval board?

     

    Thanks

    Nutan

  • AD9152-FMC    configure

    Hi ,

             I am using the AD9152-FMC chip. I now have some questions about the use of ACE. My parameters are refclk=125M,fDAC=500M  and fin=250M,however ,only when i set fDAC=125M,we  can get 500M by the DAC PLL setting. why?

    Thank you

    Coral