• RE: AD9146 quad-witch


    Our customer observes the spectrum of 4GHz with NCO only mode by AD9164-FMC-EBZ.

    A is FIR85 enable and NRZ. B is  FIR85 enable and Mix mode.

    A is more similar to Figure46(FIR85 enable and Mix mode) than B.

    Could you tell me why A is more similar…

  • AD9146 power-up time

    I have a few questions about AD9146 power-up time.
    This DAC has 260 ms power-up time.
    Why it's so much?
    Is it independent time (of operating mode, operating conditions, etc)?
    Can I reduce this time by DAC PLL turn off?

  • AD9146 Filter Taps

    Hello, I'm trying to create and extremely high fidelity model of the output signal of the AD9146. To do so, I need to know the exact filter taps of the half band interpolation filters (HB1 and HB2) and for the inverse sinc filter. The data sheet provides…

  • Questions about AD9146 frequence

    Hi Sir:



    We are surveying dual channel 1GSPS DAC for my project of network analyzer.

    But I have some questions on AD9146.


    We plan to generate DC~250MHz I/Q signal randomly.

    In AD9146 datasheet page7, I do not understand.


    If we bypass…

  • The AD9146 Filters, Premodulator and modes?

    (1) If I enable the Premodulation and set HB1 and HB2 to mode 1, do I get the
    x(t) = I(t)cos(2*PI*f*t) - Q(t)sin(2*PI*f*t), f = 125 MHz with 4 x
    interpolation at the I-DAC output, and if not, how do I setup AD9146 in order
  • AD9146 PLL Control N0 divider


    My question is about the PLL VCO N0 divider of the AD9146 DAC. In the data sheet (Rev.A page 22. PLL Control register 0x0D) are listed possible values for the N0 as 1, 2, 4 and 4. Is 4 realy the maximum value of N0 or just a typo? Could it be 8?

  • AD9146 LVDS Input Rate,DCI,fINTERFACE, and fDAC ?


    I am confused the relation between "LVDS Input Rate" and "fDAC".

    In the AD9146 datasheet,

    Table 5. Maximum Rate (MSPS) with DVDD and CVDD Supply Regulation

    Figure 30. Timing Diagram for Byte Mode

    Figure 30. Timing Diagram…

  • 请问一下AD9146是怎么配置的?


  • What is "N2[1:0] PLL control clock divider" in AD9146?

    What is it for?


  • ad9146的SED功能和FRAME信号的作用