• The AD9146 Filters, Premodulator and modes?

    (1) If I enable the Premodulation and set HB1 and HB2 to mode 1, do I get the
    x(t) = I(t)cos(2*PI*f*t) - Q(t)sin(2*PI*f*t), f = 125 MHz with 4 x
    interpolation at the I-DAC output, and if not, how do I setup AD9146 in order
    to obtain this…

  • AD9146 quad-witch


    I am FAE in Japanese distributor.

    AD9164 has 4 modes(NRZ,RZ,MIX,2xNRZ).

    NRZ,RZ and MIX are set by 0x152[1:0].

     2xNRZ are set by 0x111[0].

    When 2xNRZ(FIR85) is enable, is 0x152[1:0]  ignored or the value change the RF signal?

    Best regards


  • AD9146 Filter Taps

    Hello, I'm trying to create and extremely high fidelity model of the output signal of the AD9146. To do so, I need to know the exact filter taps of the half band interpolation filters (HB1 and HB2) and for the inverse sinc filter. The data sheet provides…

  • What is "N2[1:0] PLL control clock divider" in AD9146?

    What is it for?


  • ad9146的SED功能和FRAME信号的作用



  • RE: AD9146 PLL Control N0 divider

    The N0 divider maxes out at /4 (the data sheet is accurate) so you will need to apply one of the other means to achieve the desired DACCLK frequency.

  • AD9146 LVDS Input Rate,DCI,fINTERFACE, and fDAC ?


    I am confused the relation between "LVDS Input Rate" and "fDAC".

    In the AD9146 datasheet,

    Table 5. Maximum Rate (MSPS) with DVDD and CVDD Supply Regulation

    Figure 30. Timing Diagram for Byte Mode

    Figure 30. Timing Diagram…

  • AD9146 - How do I change the range on the auxiliary ADC used for the die temperature sensor?

    The datasheet for the ad9146 is not very clear on how to change the range on the Auxiliary ADC such that the temperature range can be modified.  In particular in the datasheet http://www.analog.com/media/en/technical-documentation/data-sheets/AD9146.PD…

  • AD9146 power-up time

    I have a few questions about AD9146 power-up time.
    This DAC has 260 ms power-up time.
    Why it's so much?
    Is it independent time (of operating mode, operating conditions, etc)?
    Can I reduce this time by DAC PLL turn off?