• RE: AD9146 Filter Taps

    Sorry, these are our design secrets and we can't reveal them to our customers without an NDA signed. Please contact our sales team directly. The will be happy to help you out with this request.

  • Using Temp Sensor of AD9122 and AD9148

    How accurate is the temperature sensor on the AD9122, AD9146 or AD9148 Dual and Quad DACs?

  • AD9146 - How do I change the range on the auxiliary ADC used for the die temperature sensor?

    The datasheet for the ad9146 is not very clear on how to change the range on the Auxiliary ADC such that the temperature range can be modified.  In particular in the datasheet http://www.analog.com/media/en/technical-documentation/data-sheets/AD9146.PD…

  • The AD9146 Filters, Premodulator and modes?

    (1) If I enable the Premodulation and set HB1 and HB2 to mode 1, do I get the
    signal
    x(t) = I(t)cos(2*PI*f*t) - Q(t)sin(2*PI*f*t), f = 125 MHz with 4 x
    interpolation at the I-DAC output, and if not, how do I setup AD9146 in order
  • AD9146 power-up time

    Hello!
    I have a few questions about AD9146 power-up time.
    This DAC has 260 ms power-up time.
    Why it's so much?
    Is it independent time (of operating mode, operating conditions, etc)?
    Can I reduce this time by DAC PLL turn off?

  • Questions about AD9146 frequence

    Hi Sir:

     

     

    We are surveying dual channel 1GSPS DAC for my project of network analyzer.

    But I have some questions on AD9146.

     

    We plan to generate DC~250MHz I/Q signal randomly.

    In AD9146 datasheet page7, I do not understand.

     

    If we bypass…

  • What is "N2[1:0] PLL control clock divider" in AD9146?

    What is it for?

    Thanks

  • RE: AD9146 LVDS Input Rate,DCI,fINTERFACE, and fDAC ?

    AD9146 is dual and 16bits DAC. The interface width is 8bits width in BYTE mode, not 16bits. So Finterface is 1200Msps, DCI is 600MHz, Frame is 300MHz for both I and Q. And FDAC max is also 300Msps.

    thanks.

  • 请问一下AD9146是怎么配置的?

    最近在使用AD9146,一直没输出,希望有人能帮帮我,谢谢@

  • AD9146 PLL Control N0 divider

    Hi,

    My question is about the PLL VCO N0 divider of the AD9146 DAC. In the data sheet (Rev.A page 22. PLL Control register 0x0D) are listed possible values for the N0 as 1, 2, 4 and 4. Is 4 realy the maximum value of N0 or just a typo? Could it be 8?