• RE: AD9146 quad-witch

    Hello

    Our customer observes the spectrum of 4GHz with NCO only mode by AD9164-FMC-EBZ.

    A is FIR85 enable and NRZ. B is  FIR85 enable and Mix mode.

    A is more similar to Figure46(FIR85 enable and Mix mode) than B.

    Could you tell me why A is more similar…

  • AD9146 power-up time

    Hello!
    I have a few questions about AD9146 power-up time.
    This DAC has 260 ms power-up time.
    Why it's so much?
    Is it independent time (of operating mode, operating conditions, etc)?
    Can I reduce this time by DAC PLL turn off?

  • AD9146 Filter Taps

    Hello, I'm trying to create and extremely high fidelity model of the output signal of the AD9146. To do so, I need to know the exact filter taps of the half band interpolation filters (HB1 and HB2) and for the inverse sinc filter. The data sheet provides…

  • Questions about AD9146 frequence

    Hi Sir:

     

     

    We are surveying dual channel 1GSPS DAC for my project of network analyzer.

    But I have some questions on AD9146.

     

    We plan to generate DC~250MHz I/Q signal randomly.

    In AD9146 datasheet page7, I do not understand.

     

    If we bypass…

  • The AD9146 Filters, Premodulator and modes?

    (1) If I enable the Premodulation and set HB1 and HB2 to mode 1, do I get the
    signal
    x(t) = I(t)cos(2*PI*f*t) - Q(t)sin(2*PI*f*t), f = 125 MHz with 4 x
    interpolation at the I-DAC output, and if not, how do I setup AD9146 in order
  • AD9146 PLL Control N0 divider

    Hi,

    My question is about the PLL VCO N0 divider of the AD9146 DAC. In the data sheet (Rev.A page 22. PLL Control register 0x0D) are listed possible values for the N0 as 1, 2, 4 and 4. Is 4 realy the maximum value of N0 or just a typo? Could it be 8?

  • AD9146 LVDS Input Rate,DCI,fINTERFACE, and fDAC ?

    Hi,all

    I am confused the relation between "LVDS Input Rate" and "fDAC".

    In the AD9146 datasheet,

    Table 5. Maximum Rate (MSPS) with DVDD and CVDD Supply Regulation

    Figure 30. Timing Diagram for Byte Mode

    Figure 30. Timing Diagram…

  • 请问一下AD9146是怎么配置的?

    最近在使用AD9146,一直没输出,希望有人能帮帮我,谢谢@

  • What is "N2[1:0] PLL control clock divider" in AD9146?

    What is it for?

    Thanks

  • ad9146的SED功能和FRAME信号的作用

    您好,我们实验室在使用ad9146的SED功能时,发现只有把比较值(0x68-0x6F)清零时才能正常工作,但是如果比较值的某一位是1,那么无论输入数据的相应位是0还是1,存储误差的相应位(0x70-0x73)都会被置1。我遇到的是不是普遍现象,或是逻辑出了问题,将异或XOR设计成了或OR关系?

    另外FRAME信号是不是起到的是对齐数据结构的作用,而不是高低电平分别代表I通道和Q通道?因为我发现FRAME始终置高电平时I通道和Q通道也是始终都有数据输入,而不是仅有I通道有数据输入。请问是不是FRAME的高电平有效脉冲起到对齐的作用…