• AD9144 - Does the AD9144 support deterministic latency/multi-chip synchronization?

    Yes, the AD9144 supports JESD204B Subclass 0 and Subclass 1 operations for deterministic latency.  Subclass 1 provides synchronization to within ½ a DAC clock period and requires a SYSREF± signal to achieve this latency variation.

  • AD9144 - What JESD204B SERDES modes are available on the AD9144?

    The AD9144 has 4 DACs and 8 available SERDES lanes with flexible interface configurations to meet various customer needs.  The table below shows the transport layer JESD204B link parameters for each mode supported.  These parameters are defined per link;…

  • AD9144 sometimes goes to blanking state

    Hello,

    we are experiencing a problem similar to the one described in this post:

    https://ez.analog.com/data_converters/high-speed_dacs/f/q-a/22410/ad9144-blanking-state-machine-behavior/412114

    we have a custom board that uses the AD9144. We were able to…

  • AD9144 output matching circuit

    Hi, 

    We are using AD9144 for prototype and I would like to know what is the purpose of this resistor R36 (25Ohm) at the center tap of the transformer and how the value is chosen. 

    Thanks in advances for your help,

    XL 

  • AD9144: Need help in testing for PRBS

    Hi team

    I am looking to test AD9144 for PRBS7. For this, I am sending 32 bit PRBS7 data across 4 lanes (same data on 4 lanes) from the FPGA. On the AD9144 side, I am following Device Setup Guide section of AD9144 data sheet for details on setting up the…

  • FMCDAQ2 AD9144 JESD204B Modes 7

    Hi,

    My requirements are:

    - JESD204B operating mode 7 (LMFS=1241)

    - DAC sample rate 250 MSPS

    - Interpolation factor 8

    - NCO 75 MHz

    For now, I will configure the board without interpolation and NCO to make sure everything is set correctly.

    Setup Environment…

  • DAQ2-ad9144: SYNC asserted & Link status CGS

    Hi

    Setup Environment:

    Evaluation Kit: iW-RainboW-G35M

    FPGA Package: xczu19eg-ffvc1760-1-i

    Vivado/Vitis Version: 2020.1

    Git Hub: master (HDL & no-OS) - Cloned on 9 June 2022

    Requirements:

    - ADC sampling rate 750MSPS - decimation is x2 - two channels (use…

  • AD9144 even harmoics too high

    Hi,

    At our design we terminate AD9144 DAC outputs to 50ohm resistors to gnd, each. In our test we create CW square wave by toggling DAC output high and low at 237Mhz. We are measuring with spectrum analyzer on AD9144 50ohm outputs while all the rest of…

  • RE: AD9144 unexpected power-down

    Assumed answered offline.  Please re-submit if problems persist.