• AD9144 - Does the AD9144 support deterministic latency/multi-chip synchronization?

    Yes, the AD9144 supports JESD204B Subclass 0 and Subclass 1 operations for deterministic latency.  Subclass 1 provides synchronization to within ½ a DAC clock period and requires a SYSREF± signal to achieve this latency variation.

  • AD9144 - What JESD204B SERDES modes are available on the AD9144?

    The AD9144 has 4 DACs and 8 available SERDES lanes with flexible interface configurations to meet various customer needs.  The table below shows the transport layer JESD204B link parameters for each mode supported.  These parameters are defined per link;…

  • AD9144 unexpected power-down

    At the final write in the flow (write 0x01 to reg 0x300), I find that I sometimes need to write to it twice to actually read 0x01 from it.

    Regs 0x470-0x473 are all reading 0xFF, which is good!

    But on the output of the DAC we see inconsistencies. We see…

  • RE: FMCDAQ2 AD9144 ILA error

    Hi,

    Sorry for the delayed reply. We somehow missed your reply.
    The question regarding the OS(Linux or no-OS),  we are interested on the FPGA side.
    Have you found the cause of your problem?

    Andrei

  • AD9144

    AD9144

     

    I am trying to set up the AD9144 DAC registers but there are some questions that I would like answered and I was hoping that someone in the community has had previous experience with the AD9144 DAC registers.

     

    I will list the questions that…

  • RE: AD9144 SFDR on FMCDAQ2, poor SFDR due to distortion for > -3dBFS

    The analog devices driver for the ad9680 leaves the digital gain setting at the standard value of 2.7dB. This is considered to be used for 2x interpolation. To use a 1 GHz Sampling clock with no interpolation, the gain should be reduced to 0 or turned…

  • AD9144 configuration sequence and PRBS test

    Hi,

    I am trying to configure the AD9144 to single-link, PLL bypass, clock @237.6MHz.

    I need some help with the DAC AD9144 configuration. Maybe I'm missing some registers configuration that are not in the Spec. I am following the Spec flow.
    I have reached…
  • AD9144 revision

    Hi,

    I have build a system using AD9144 JESD DAC.

    The version populated on my PCB is rev 0x02. (Read from register adress 0x06 field DEV_REVISION).

    So far, I have been using datasheet rev 0, which also confirms that value.

    I recently downloaded an…

  • AD9144

    Hi sir,

    I would like to use a quad high speed DAC to drive two IQ modulator ADL5375.

    I need to send 130Ms/s to each DAC input. I need DAC oversample x2 the inputs, so each DAC frequency sampling would be 260Ms/s.

    Both IQ pair must be perfectly synchronous…

  • ad9144 configuration

    hi sir. this is vinay. am using AD9144(DAC) interfacing with kcu105 fpga board. how to configure ad9144.

    i need 140 MHz output from ad9144...how to get this frequency from ad9144 sir...High-Speed DACs