Hi
Has anyone had a problem with the AD9136 configuration? I configure register 0x453 to descramble data from JESD, but it does not descramble them. ADC processes clean data. When I read this register, the data in it is ok (0x80).
I am sending configuration…
The ADI App Note "Validating ADI Converters inter-operability with Xilinx FPGA and JESD204B IP" states that "Each converter device requires its own FPGA firmware." Can I get the FPGA firmware source code for the AD9136? Also, is it OK to violate the SYSREF…
There are two evaluation boards available for the AD9135/AD9136:
AD9135-EBZ
AD9136-EBZ
DAC Only Evaluation Board [DPG3 Compatible]
AD9135-FMC-EBZ
AD9136-FMC-EBZ
DAC Only FMC Evaluation Board [FPGA Compatible…
Hi Michael,
I am using AD-FMCDAQ2 files on KC705 to setup my AD9136. I can now access the registers via SPI and able to communicate with AD9136, but when I try to change register 0x459 to 0x21 the DAC PLL does not get locked.
Also what parameters I…
Hi Istvan,
Also what parameters I need…
The AD9135/AD9136 are the industry's highest signal bandwidth dual d/a converters. In 1x interpolation mode, the user can utilize the full JESD204B data interface bandwidth in the AD9135/AD9136 to generate signal bandwidth up to 1.06GHz per DAC…
The AD9136 and AD9144 product pages have been updated to include a link to their respective IBIS models. This bug has been corrected. Please go to their product pages (links below) and click the IBIS model link:
AD9144: www.analog.com/ad9144
AD9136…
Hi,all.
I am checking the PCB pattern connect of AD9136 FMC EVALUATION BOARD.
I can not understand the connect from the FMC to the SERDINx+/-.
Is it typo?
In the sheet 4 of 8, @ AD9136-FMC-EBZ RevB Schematic.pdf ,
SERDINx+/- (FMC?) is cross…
SERDINx+/- (FMC?) is cross or straight…
Hi,
I am using AD-FMCDAQ2 files on KC705 to setup AD9136. I am just using one DAC on AD9136 at the moment. I can access the registers via SPI and able to communicate with AD9136, but when I try to change register 0x459 to 0x21 the DAC PLL does not get…