Hi， by 1x mode, bypass filters/modulator, the latency will be 64 DAC clock cycle, see datasheet page5.
Is it possible to use AD9125 IN NON-I/Q mode ?
Dear Team, One of our customer have the next problem with DAC9125, can you please help us?
We are using an Analog Devices AD9125 DAC.
It is operating at 100 Msps baseband sampling frequency. We are using 8x interpolation and the coarse mixer to upconvert…
1. We are able to configure the PLL AD9516 to generate required clocks for DAC AD9125 chip( REF CLK, DAC CLK).2. Digital data along with clock is given through FPGA.3.DAC is configured through SPI using register configuration given in ACE GUI software…
Hello I have a development running inside a design house and I have been asked for this support:
They are trying to use the internal NCO from the DAC to shift the frequency of the input sine wave.
With that it would be possible inject a sine to 7.8125Mhz…
I'm using AD9125 to generate a complex signal at 70MHz.
Is it possible to achieve image suppression @ the O/P if I'm feeding a complex IF signal to the DAC and use the complex mixer to generate the O/P?
From the DUC I'll generate the complex…
One of my customers is designing RF transmitter by using AD9125 DAC.
His baseband frequency bandwidth is 26.6 to 45.6MHz.
Output RF signal should be 76MHz to 95MHz.
Clock frequency is 121.6MHz.
HB1 Control register is set as 10 (0.6…
We are using AD9125 for our communication system transmitter.
The upconversion to IF is also done using the complex mixer within the DAC.
The reference clock to DAC ia 100MHz and we use the internal PLL to generate the internal DAC sampling clock…