The fifo thermometer readback always returned 0x55 indicates the AD9122 is either not getting a DACCLK signal or you are holding the part in osft reset. Since the Sync register is not changing I expect you are not getting a DACCLK to the AD9122.
Have a look at the AD9122 datasheet - it requires a DDR interface - check out Figure 46. Timing Diagram for Input Data Port (DCI is the Data Clock Input from the PFGA)
Frequency of the baseband signal is DC~110MHz, Sample frequency is 300MHz, LVDS interface rate of AD9122 is 600MSPS, we want to use x4 interpolation, how to set up HB filters of AD9122?
Hi Biao Huang,
You can find below my test process on AD9122 component. On my board, I have two AD9122 components.
1/ AD9122 components are connected to Xilinx FPGA (xc5vsx95t).
All the data pins are always level high.
FRAMEP = ‘0’ and FRAMEN = …
1. The AD9122 core is just an interface core, which ease the access to the AD9122 device, so you should use this core either way. The question is where do you want to implement your modulation algorithm, in software or hardware. If in software…
I am using the xilinx board KCU105 to generate the Baseband signal ，and need a DAC to converter the Baseband I/Q data ，then the Analog signal is send to the IQ modulator。
And I am looking some DACs（such as AD9122 、AD9142A），and have some question…
Now it leaves the probe function with cf_axi_dds: probe of 9c524000.cf-ad9122-core-lpc0 failed with error -1..
It fails in ad9122.c in the ad9122_tune_dci function on the line
if(!(reg & (AD9122_SED_CTRL_SAMPLE_ERR_DETECTED | AD9122_SED_CTRL_COMPARE_PASS…
For accessing the AD9122 registers you can use ad9122_write() (no-OS/AD9122.c at master · analogdevicesinc/no-OS · GitHub) and ad9122_read() (no-OS/AD9122.c at master · analogdevicesinc/no-OS · GitHub) functions. For example: