What is the Maximum input data rate the AD9122 can handle and what is the maximum bandwidth the AD9122 can support?
I am using AD9122 with 210MHz frequency with bypassed interpolation in Byte mode, how can i get to know the maximum frequency for DCI signal. Thanks inadvance.
I designe a system using the AD9122.
But i can't find a analog and digital power domain in AD9122 datasheet.
I saw a figure that is divided into analog domain and digital domain at AD9788 datasheet.
(show on page 11 in AD9788 datasheet)
Sloved. Thanks for your information.
On my board, I have two AD9122 components.
I program the component with the below registers:
0x0D = 0xD6
0x0A = 0xF8
0x08 = 0xFF
0x1C = 0x04
0x1D = 0x24
0x1E = 0x12
All the others registers are the default value.
The ouput power is different…
Is there any manual available, explaining all the variables in the AD9122-25 Customer SPI Rev15 software which comes together with the DAC Suite?
This question applies to AD9122.
About Register 0x00 RESET and pin54 /RESET,
Is there a minimum RESET pulse width for initialization of these?
Also, after RESET is released, how long until the chips can be programmed via SPI?
I tried to make datapath configuration for ad9122 but I could not understand how to set interpolation filter modes. Our setup block diagram is in below. DCI port freq is 246.76 MHz and 16 bit QPSK data is send to ad9122+adl5375 eval board…
I had a question regarding supported bandwidth and interpolation rates as mentioned in the AD9122 datasheet, Table 22.
I am interested in using the 16-bit Word input bus and interpolation by 2 (only HB1 is enabled). The table 22 shows fdata =…
I am using zedboard with fmcomms1. I am using the HDL reference design from the analogdevicesinc/hdl · GitHub
I was trying to understand how the clock is running between zedboard PL and fmcomms1. The port ref_clk which is clock of 30.3 MHz is routed…