If we cold star with AD9119, PLL LOST will occur.Even if the initialization sequence was executed again, it remained PLL LOST.What kind of solution is there?
When will be the AD9119/AD9129 and the associated eval board available ?
We use AD9119 output 32 channel J83 QAM signal, most time it"s good:
but some times the 9119 output like this:
Can anybody give us some ideas?
I'd like to ask you about I250U in AD9119.Q1.In Figure1 for datasheet, I250U connected 1.2V.What does it mean?Q2.Pls check Figure1 and Figure149.They have some differences around I250U, VREF and the comparator.Which is correct?Q3.Description…
Figure 148 in AD9119 datasheet shows a possible signal chain for the clock path base on ADF4350 PLL usage.
Figure 22 in ADF4350 datasheet shows the PLL output stage.
In my opinion, biasing is missing on the ADF4350 side since its output stage do not…
We are planning to operate the DAC with the sampling rate of 2.7 GHz and in second nyquist using Mix mode.
1) So we would like to know whether the part is capable of supporting instaneous bandwidth of 1 GHz (1.5 GHz to 2.5 GHz)
I can't find DC specifications (Vih, Vil, Vol, Voh, leakage, and so on) for RESET and IRQ pins in the datasheet.
In addition, there are two different indications about the pull-up value to use on IRQ pin (1k on p.9 and 10k on p.47).
If a pull-up…
I am interested in using the AD9119 with a Xilinx Virtex 7.
I want to generate waveforms using the Xilinx.
I found the following set up on your WIKI site where the AD9129 works with a
Xilinx ML605 board :
I`m wondering if one can use the AD9119/9129 with I/Q (interleaving) input data?
Thanks a lot!