• RE: AD9116 DCLKIO CLKIN shared data bus and simultaneous synced output

    Hello Mark,

    Yes, I think it will work. You might need to tinker with Retimer register 0x14 though.

    On the bottom of your drawing, DAC1 DCLKIO is aligned with CLKIN. I think you want to delay that until after CLKIN to avoid the possibility of DAC1 come…

  • AD9117: How do I estimate the overall DAC pipeline delay?

    How do I estimate the overall DAC pipeline delay?

     

    DAC pipeline latency is affected by the phase of the RETIMER-CLK that is
    selected. If latency is critical to the system and must be constant, the
    retimer should be forced to a particular…
  • ADI公司解决方案通报—数模转换器IC

    目录


    • 提供动态功率控制的DAC
    • 低功耗DAC可节省功率
    • 突破性1 ppm DAC
    • 基站发射架构中的IF DAC解决方案
    • 新款DDS IC功耗更低、尺寸更小
    • 多路输出低抖动时钟发生器
    • 数据转换知识资源
    • 低功耗精密运算放大器用作DAC缓冲器
    • 选型指南
    • RF DAC实现单封装比特流到射频转换解决方案
    • 用于无线通信设备的混合信号前端IC
    • 采用WLCSP封装的8通道denseDAC .
    • 采用紧凑型封装的多功能、易用、精密DAC
    • 新型系…
  • AD9717 and AD9117 CML Pins

    What is the purpose of the CMLI and CMLQ pins on the AD9717 and AD9117 DAC famlies and where do they need to be connected?

  • DAC Calibration

    Some high speed DAC have options for auto-calibration. Why and when should I use this option?

  • TAGS LIST: Data Converters

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    AD5421
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    AD5593R
    AD5592R
    AD5940
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    AD7293
    AD7294-2
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    L…