• DAC AD9115 with ADRF6720-27

    I have implemented the DC blocking capacitor as shown on a previous post to create the level shift at 2.7V.

    https://ez.analog.com/rf/f/q-a/72214/adrf6720-27-rfoutput-problem/168465#168465

    I am seeing some ringing on the Vector Signal Analyzer on the burst…

  • RE: AD9761 and AD9763

    The AD9115 and AD9715 are 10 bit dual 125MSPS worth looking at.

    Someone from the HDMI group needs to address the AD9883.

    Thanks,

    Larry

  • AD9115 Not Recognize 1.8V DATA INPUT

    Hi, dear ADI engineers, we built an AD9115 prototyping board with following power settings:

    AVDD = 3.3V

    DVDD = DVDDIO=CVDD=1.8V

    The clk signal is from a clk chip's LVCMOS18 output, and we feed DCLKIO to FPGA. The FPGA reconginzed the CLK and output…

  • TxDAC for video application

    Hi,

    I consider using a TxDAC AD9115 as a video DAC to produce 2 channels of NTSC composite video. The advantage of the TxDAC is it's high bandwidth and small PCB footprint, all the color modulation and sync will be done in FPGA. Does anyone has an experience…

  • AD9115: Limit for the current the part can deliver

    We have seen that the datasheet has been recently updated. Therefore, I want to
    ask you about one parameter that has changed. In Table 1, for AVDD=1.8V, the
    full scale output current max is now 8 mA, when in the previous version of the
  • AD9115 (AD9114 AD9116 AD9117) SPI Port Problems

    We have built a prototype board using the AD9115 DAC and I’m trying to configure it using the SPI port and am having trouble.  Here’s what I’m doing and what I’m getting:

     

    • I power up the DAC and then toggle the RESET/PINMD pin from low to high to…
  • AD9116 questions & datasheet errata

    I'm working on a design using the AD9116.

    I would like to tie the power pins to:

    • AVDD = 3.3v supply
    • DVDDIO=CVDD = 2.5v supply
    • DVDD = bypass cap only (no external load or supply)

    I would then use 2.5v signals (Xilinx V6 LVCMOS25 outputs…

  • AD9117: How do I estimate the overall DAC pipeline delay?

    How do I estimate the overall DAC pipeline delay?

     

    DAC pipeline latency is affected by the phase of the RETIMER-CLK that is
    selected. If latency is critical to the system and must be constant, the
    retimer should be forced to a particular…
  • AD9114/5/6/7 output stage voltage compliance

    I have a question regarding the main DAC output of the AD9114 / AD9115 / AD9116 / AD9117.

    Power is +3.3 V and for many reasons (cost, space, voltage supply and others) we need to get as much power as possible from the output stage to avoid an extra amplification…