• AD9083 dev-board layout in *.BRD

    Hello,

    I am working on a design utilising AD9083. Could you please share with me the dev-board's layout in *.BRD?

    Many thanks in advance!

    Best regards,

    Krzysztof

  • RE: AD9083 on ZCU102 HDL reference design

    Hello, 

    looks like the vivado process is killed.

    [Sat Sep 4 13:27:46 2021] Waiting for synth_1 to finish...
    /media/kashima/LinuxVivado20.2/tools/Xilinx/Vivado/2020.2/bin/loader: line 309: 23727 Killed "$RDI_PROG" "$@"

    The build should…

  • RE: AD9083 for Intel FPGA

    Hello,

    We have a plan to support AD9083 on Intel devices, but I cannot say when it will be available, maybe in the next couple of months.

    You could start from https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/a10soc adn use https://wiki.analog…

  • RE: [AD9083] Using fewer than 16 channels in nonburst datapath, NCO enabled?

    Please see table 24 of the datasheet. When using the NCO/Mixer, the only M value supported is 32. You should be able to get more bandwidth from using 12 bits of resolution. Would that work in your application?

  • AD9083 API Register Writing

    Hi!

    We are considering using the AD9083 device for our project. We have the API Device Drivers, and we want to export the API configuration functions to implement them in HDL for an FPGA. Looking for each of the register writing for the device configuration…

  • AD9083 pulse sampling mode

    Hello,

    I am thinking about using the AD9083 ADC in a new design but I am not sure if it is suitable for my application.
    So far I have only used flash/pipelined ADCs (AD9234, AD9694, ...) and I am not very familiar with the sigma-delta method.
    I want to use…

  • IP JESD204B for AD9083

    Hi,
    I should interface a genesys 2 FPGA board(which supports speeds up to 10.3 Gb/s) with an AD9083(obviously I don't need to use the maximum speed), I'm using vivado and I tried to use the IP core JESD204 from Xilinx, but it seems not to work and I don…

  • IP JESD204B per AD9083

    Hi,
    I should interface a genesys 2 FPGA board(which supports speeds up to 10.3 Gb/s) with an AD9083(obviously I don't need to use the maximum speed), I'm using vivado and I tried to use the IP core JESD204 from Xilinx, but it seems not to work and I don…

  • RE: AD9083 : Analog input characteristics (STF)

    The STF will vary depending on the way that the AD9083 is configured. The sample rate, low pass filter, CIC decimator and decimate by J filter will all contribute. Is there a particular configuration or frequency range that you are interested in?

  • ADS8-V3EBZ buffer size with EVAL-AD9083

    I have a question about how long of a data stream I can capture using EVAL-AD9083 ADC Board on an ADS8-V3EBZ FPGA Controller Board.

    The ADS8-V3EBZ wiki page mentions that it has a:

    >Dual-bank DDR4 SDRAM
    What is the total size of the RAM. Is this soldered…