• AD9083 BCENTER_OFFSET register?

    The BCENTER_OFFSET register in the AD9083 is not part of the documentation except that it "sets the offset value for Bcenter". What does it do?

  • AD9083 Absolute Time Tagging

    I am evaluating the AD9083 for use in an application where tagging the data stream with high-precision (~ 1 ns, ideally better) absolute times is important. The easiest way to do this seems to be using the SYSREF input on coarse boundaries (e.g. 1PPS…

  • AD9083

    Hello, I am a software engineer. I have some problems when using ad9083. I want to ask you for advice.

    Hardware environment: use DSP with 204b interface to connect with ad9083, in which ad9516 provides 250m clock to ad9083.

    Question: I found the ad9083…

  • AD9083 configuration

    Here are my configuration parameters:

    datapath:ADC-J

    Sample rate = 1 GSPS.

    NCO/mixer bypassed

    CIC bypassed

    J=8

    L=4

    M=8

    F=4

    S=1

    N'=16

    N=16

    CS=0

    CF=0

    K=32

    status register 0XD44 and 0X301 both are display PLL is locked ,but AD9083 is still not work.why…

  • PLL of AD9083

    Hardware environment: DSP with 204b interface is used to connect with ad9083, in which ad9516 provides clock for ad9083.


    Software environment: according to the official driver of ad9083, when the link rate is configured as 15gbps, 7.5gbps and 3.75gbps…

  • AD9083 API drivers

    Q1:When using the official device manual and driver, it is found that the registers mentioned in the driver are not covered in the manual. For example, in ADI_ ad9083_ rx_ adc_ config_ set (), 0xb96, 0xb97 and 0xb98 registers are operated, but these registers…

  • JESD204 setting for ZCU102+AD9083 HDL reference

    Hi all,

    I'm using AD9083 on ZCU102 HDL reference design (wiki.analog.com/.../ad9083_evb_reference_hdl) with .

    Linux driver, and trying to modify it so that the sampling rate per converter becomes 160Msps as follows.

    AD9083 EBZ setting in dtsi:

     -…

  • Debugging AD9083-ZCU102 HDL reference design with iio

    Hi all,

    I'm trying to use AD9083 on ZCU102 HDL reference design (wiki.analog.com/.../ad9083_evb_reference_hdl) with Linux driver.

    To confirm the data acquidition from ADC board, I tried following steps after boot.

    1. Enable channels

      echo 1 > /sys/bus…

  • rootfs.cpio for AD9083 on ZCU102 HDL reference design

    Hi all,

    I'm trying to use AD9083 on ZCU102 HDL reference design (wiki.analog.com/.../ad9083_evb_reference_hdl) with .

    Linux driver.

    Since META-ADI-XILINX does not support this HDL project, I used script method for zynqmp (https://wiki.analog.com/resources…

  • ADI JESD framework: different PRBS sequences between AD9083 and TPL RX

    Hey everybody,

    We've been eyeing ADI's JESD framework at the GitHub repo as an alternative to Xilinx's framework to be implemented using an AD9083 + Zynq MPSoC.

    We saw that the Pseudo Random sequences produced by the AD9083 used to verify the…