• Setup time of AD9081?

    What is the setup time of the AD9081? Does it vary over temperature or any other external factors?

    Page 29 of the user guide provides the keepout window (KOW) that sums the hold time and setup time to be 142 ps, but I can't find what the individual contributions…

  • AD9081 NCO Test Mode

    I am trying to use the ACE GUI to simply use only the NCO to generate a CW tone. I select NCO Test Mode and direct clock at 12GHz. I also feed a 375MHz clock into the JESD clock input on the ADS9 to match the settings in the GUI. I don’t know if this…

  • AD9081

    Hi,

    I am reviewing on AD9081 design and having some doubts. Appreciate if ADI can provide some advice.

    In datasheet of AD9081, the maximum speed of SERDES JESD204B interface is 15.5Gbps. Might I know if you have any advice regarding to the high speed…

  • AD9081 FMCA EBZ + ZC706 clocking

    Hi,

    I have a AD9081-FMCA-EBZ mounted on a ZC706 board. I'm trying to set the data rate for TX and RX as slow as possible. The purpose is enable the transmission of data via Ethernet (limited bandwidth), without developing an extra interpolator and decimator…

  • Logical lane mapping for AD9081

    Hi everyone,

    I have a question regarding logical lane mapping in the app_config.h for ad9081 device. On the website page: link under software consideration the logical lane mapping is different as described in the app_config.h for AD9081. Also how is it…

  • Memory Map does not change in ACE.(AD9081)

    Dear Sir or Madam

    I would like to control ad9081 using xilinx's Kintex.

    The memory map of the other chips of the ACE is changed according to the set value, but ad9081 is not changed.

    There are more than 16,000 rem all myself and change them?

    Or is…

  • How do I calculate the loop filter value for AD9081?

    Hi

    I would like to make the VCO output 12GHz by setting AD9081 as below.

    Fin => 100MHz, Mvco => 5, Nvco => 24, R => 1

    However, it is monitored that SLOW LOCK does not work at all and FAST LOCK continues to unravel.

    Do you have any calculation…

  • AD9081-FMCA-EBZ-A3 & VCK190 JESD Initialization

    I am trying to bring up the AD9081-FMCA-EBZ-A3 board with the versal VCK190. but am running into issues with the JESD initialization.

    I've been using the prebuilt files from the versal-vck190-reva-ad9081 and versal-common directories on the latest SD…

  • AD9081 HDL Reference Design for real-time applications

    Hi,

    I want to use the VCU118 FPGA kit to capture the signal from AD9081. I saw that in your reference design for AD9081, data captured from AD9081 is stored in DDR4. But in my application, I want to stream real-time data from AD9081 (FPGA) to PC for real…

  • RE: PN of AD9081 on AD9081-FMCA-EBZ?

    the AD9081 has two flavours: -4D4AC and -4D4AB. the -4D4AB is a limited option variant of the -4D4AC. more details on the part numbers are available in the datasheet ordering guide

    the Eval Board ships with the -4D4AC.