• AD7961: FAQs

    Are the design tools such as IBIS model, FPGA reference design and CFTL
    available for the AD7961?


    Yes, please follow the link below:

  • AD7961 CODE

    module ad_ok3(
            input           clk,                    // 100 MHz Clock, used for tiing
            //input           clk,                 // (Maximum 300 MHz Clock, used for serial transfer)  100MHz
            input           rst_n,             …

  • AD7961

    I'm confused ...

    The manual states:
    The CNV± pulse must be returned low (≤tCNVH maximum) for valid operation.

    I understand that I have to create a pulse that should be at least 10 nsec and shouldn't be longer than 120 nsec.

    After a conversion…

  • AD7961 - power supply sequence

    Q: Is there a power-up sequence that I should follow in operating the AD7961?

    A: When powering up the AD7961 device, first apply 1.8 V (VDD2, VIO) to the device, then ramp 5 V (VDD1) and apply an external reference voltage. Apply the analog inputs last…

  • What is AD7961?

    What is AD7961?


    The AD7961 16-bit, 5-MSPS PulSARRegistered differential ADC, uses a capacitive 
    digital-to-analog converter (CAPDAC) based successive-approximation register
    (SAR) architecture to provide the unprecedented speed, noise and linearity

  • AD7961 TIMING

    The timing of cnv and clk is ok?

  • Evaluation board for the AD7961

    Is there an evaluation board for the AD7961?


    Yes, the EVAL-AD7961MCZ board can be used to evaluate the AD7961 part, which is
    compatible with the System Demonstration Platform (SDP) board - EVAL-SDP-CH1Z.
    Refer to UG-581 for complete information…

  • AD7961 input structure


    As you know, based from the datasheet of AD7961,the input type is differential. can it be used as single-end input? It means that the IN- connect to GND,only the IN+ used as the input terminal.

    Is it Ok?


  • AD7961 Reference help



    I have been working on using the AD7961 A/D on the Zedboard (Using Zynq Chip) and have come across some errors I cannot figure out.


    I am using the reference design from analog's wiki page


  • AD7961 DC setup

    Dear experts,

    I am using the eval board ad7961, using the opamps, with Zedboard. Considering the scenarios below I can only get results which make sense in the A.2. I attached the results. The amplitude is 0 to 65535 (2-complement considered). The En…