The clk should be sent after 200ns? I will try.
input clk, // 100 MHz Clock, used for tiing
//input clk, // (Maximum 300 MHz Clock, used for serial transfer) 100MHz
input rst_n, …
I'm confused ...The manual states:The CNV± pulse must be returned low (≤tCNVH maximum) for valid operation.
I understand that I have to create a pulse that should be at least 10 nsec and shouldn't be longer than 120 nsec.
After a conversion…
Q: Is there a power-up sequence that I should follow in operating the AD7961?
A: When powering up the AD7961 device, first apply 1.8 V (VDD2, VIO) to the device, then ramp 5 V (VDD1) and apply an external reference voltage. Apply the analog inputs…
As you know, based from the datasheet of AD7961,the input type is differential. can it be used as single-end input? It means that the IN- connect to GND,only the IN+ used as the input terminal.
Is it Ok?
I have been working on using the AD7961 A/D on the Zedboard (Using Zynq Chip) and have come across some errors I cannot figure out.
I am using the reference design from analog's wiki page
I am using the eval board ad7961, using the opamps, with Zedboard. Considering the scenarios below I can only get results which make sense in the A.2. I attached the results. The amplitude is 0 to 65535 (2-complement considered). The En…
Please teach me GND layout of AD7961.
AD7961 has 3REF_GND(Pin No.26,27,28) , 2GND(Pin No.13,24) and EP(Pin No.33)
Which pin is digital GND?
Which pin is analog GND?
What's are connected internally?
Does it be better characteristic to connect…
I recently downloaded the AD7961 reference design from the Analog WIKI (AD7961 Native FMC Card & Xilinx Reference Design [Analog Devices Wiki]) using the Echoed Clock variant.
Diving into the Verilog code provided for the AD7961, I see the design…