• AD7770 irregulare result every few samples

    We use the AD7770 to sample 8 input channels very accurate. 

    We configure the AD7770 and release it to sample on 1Khz base. Also set GENERAL_USER_ CONFIG_3, Bit 4 to readback the sigma delta. We get the DRDY as expect and after each one we read the result…

  • /START in AD7770,AD7771, AD7779

    In the datatsheet description of AD7771, /START is tied to DGND if it is NOT used.

    On the other hand, in the datasheet description in AD7770 and AD7779, /START is tied to IOVDD if it is NOT used. 

    CAN I connect ~START to IOVDD when I don't use it?

  • AD7770 SPI MISO Always Gives 0x20

    We are using an STM32 board to communicate with AD7770 using SPI. As shown in the attached picture, the MCU is providing the correct clock, MOSI, and CS. However, the ADC MISO is always 0x20, regardless of any changes. This is shown in the attached oscilloscope…

  • AD7770 values contains modulated high power noise

    We have AD7770 running at 32 KSps, SPI mode, single-ended. For testing, we feed in pure sine wave (for example 440Hz) into a single channel. Output values contains high pitch noise, after FFT it shows we have 2 strong (and sharp) peaks at 8 KHz and 16…

  • Sport Interface DSP between BF607 and AD7770


    I have a DSP BF607 connected to a AD7770 (using one SPI interface for configuration, and one SPORT interface for data acquisition.

    SPI Configuration is all good. It is configured in mode 00 (4 DOUT lines enabled, outputing two channels per line).

  • AD7770 Always runs in low resolution mode

    I am trying to connect AD7770 (on Eval-AD777xCMZ board) to ARM M4 microcontroler on STM32F407 board and use it in HIGH RES mode. So far I managed to read and write to registers on AD7770 but the problem is AD7770 gives me 8kHz signal on DRDY pin regardless…

  • AD7770 Evaluation Board: No DRDY pulse after RESET pulse.

    I'm using the AD7770 Eval Board. The Main Supply of the board is from the 9V external Wall Adapter and I want to get ADC data to Altera FPGA board  through J1 header ( SPI mode)

    However, after the power up the DRDY signal is always at LOW state. I…

  • EvalBoard AD7770 - Connect the AINx- signals together to ground


    I'm using the Eval Board of AD7770.

    Is it possible to configure the 8 AINx- channels together to AGND ground?

    Thank you for your answer,

    Best regards

  • Example of code C to the AD7770 SPI


    I search some example code to drive the AD7770 SPI. 

    thank you for your answers.


    Best regards.

  • AD7770  Delay from SYNC_IN to first DRDY

    I'd like to know how to estimate the delay from SYNC_IN pulse to first DRDY. I guess it depends on ODR and mode. But the conditions of tINIT_SYNC_IN are only 16 kSPS, high resolution mode. And I'd like to know from what timing the delay have to be estimated…