• AD7770 clock not switched over

    Hello, I am using an AD7770 ADC and I am getting the error "Clock not switched over" in the bit 4 of the GEN_ERR_REG_2 register. Is this because my clock source doesn't work or could it be because of something else? Any way to fix it?


  • AD7770 Error misunderstanding

    Hello all.

    I found some misunderstand error flages active.

    1. We connect ch5 input with 2 DC signal. one is 1V on the positave side and one is 200mV on the negative one. We read the result correct on the output. But when we look on the error register…

  • Spi mode of AD7770

    In the page 39 of AD7770 datasheet, there is an illustration that shows that the -CS, SDO, SDI and SCLK are to be connected to the FPGA or DSP.   My question,  is the SPI in AD7770 act as a slave when connected to the FPGA or DSP?

    It means the SPI in the…

  • AD7770 When do 'EXT_MCLK_SWITCH_ERR' occur?


    When do 'EXT_MCLK_SWITCH_ERR' occur?

    How long should the external clock not switch?

    What is the reference point where 'EXT_MCLK_SWITCH_ERR' occurs?

  • curious about ad7770 'CLK_QUAL_DIS' register.


    I am using 7.68MHz for mclk.

    And then i'm try to 'clock modulation' mclk.

    Therefore, i'm try to disable 'CLK_QUAL_DIS' so that 'EXT_MCLK_SWITCH_ERR' is not set.

    However, the datasheet says that the CLK_QUAL_DIS setting…

  • AD7770 / AD7771 / AD7779 Evaluation Board


    I am interested in using the AD7770 / AD7771 / AD7779 Evaluation Board as DAQ-System. Unfortunately, I cannot find any information regarding the software's capability of acquiring data continuously, without missing samples. Is that possible and can…

  • /START in AD7770,AD7771, AD7779

    In the datatsheet description of AD7771, /START is tied to DGND if it is NOT used.

    On the other hand, in the datasheet description in AD7770 and AD7779, /START is tied to IOVDD if it is NOT used. 

    CAN I connect ~START to IOVDD when I don't use it?

  • AD7770 irregulare result every few samples

    We use the AD7770 to sample 8 input channels very accurate. 

    We configure the AD7770 and release it to sample on 1Khz base. Also set GENERAL_USER_ CONFIG_3, Bit 4 to readback the sigma delta. We get the DRDY as expect and after each one we read the result…

  • AD7770 SPI MISO Always Gives 0x20

    We are using an STM32 board to communicate with AD7770 using SPI. As shown in the attached picture, the MCU is providing the correct clock, MOSI, and CS. However, the ADC MISO is always 0x20, regardless of any changes. This is shown in the attached oscilloscope…

  • AD7770 values contains modulated high power noise

    We have AD7770 running at 32 KSps, SPI mode, single-ended. For testing, we feed in pure sine wave (for example 440Hz) into a single channel. Output values contains high pitch noise, after FFT it shows we have 2 strong (and sharp) peaks at 8 KHz and 16…