• AD7779 and AD7770


    I have a question about a differencis of digital flter between AD7770 and AD7779.
    Attached file is the rms noise and resolution performance table from the datasheet.
    AD7779 and AD7770 have same combination of ODR and Decimation Rate excluding 32kSPS…

  • AD7770 memmap crc error


    I use AD7770 with variable sps, and set new sps value approximately every 2ms. 

    Measurements are correct, but the ADC produces an error MEMMAP_CRC_ERR.

    Any other error flags is zero (Including any SPI errors).

    According to the documentation, I have…

  • AD7770 sampling progressing signals

    Hello all.

    I want to use the AD7770 to sample a precise point in input signal. I have 1 DAC that change the test signal for different level, and I do a single measure to each point.

    There is no information on the AD7770 datasheet about the process of…

  • AD7770 increasing ENOB

    We use TIA (current to voltage) very low noise and we want to get 20 ENOB. As I see in table 26 of the AD7770 datasheet we need to use 2000 SPS to get 19.77. But if we go to 8000SPS we get 18.76 which is only 1 bit less, so if I use oversample of 2^1=2…

  • AD7770 clock not switched over

    Hello, I am using an AD7770 ADC and I am getting the error "Clock not switched over" in the bit 4 of the GEN_ERR_REG_2 register. Is this because my clock source doesn't work or could it be because of something else? Any way to fix it?


  • AD7770 Error misunderstanding

    Hello all.

    I found some misunderstand error flages active.

    1. We connect ch5 input with 2 DC signal. one is 1V on the positave side and one is 200mV on the negative one. We read the result correct on the output. But when we look on the error register…

  • Spi mode of AD7770

    In the page 39 of AD7770 datasheet, there is an illustration that shows that the -CS, SDO, SDI and SCLK are to be connected to the FPGA or DSP.   My question,  is the SPI in AD7770 act as a slave when connected to the FPGA or DSP?

    It means the SPI in the…

  • AD7770 When do 'EXT_MCLK_SWITCH_ERR' occur?


    When do 'EXT_MCLK_SWITCH_ERR' occur?

    How long should the external clock not switch?

    What is the reference point where 'EXT_MCLK_SWITCH_ERR' occurs?

  • curious about ad7770 'CLK_QUAL_DIS' register.


    I am using 7.68MHz for mclk.

    And then i'm try to 'clock modulation' mclk.

    Therefore, i'm try to disable 'CLK_QUAL_DIS' so that 'EXT_MCLK_SWITCH_ERR' is not set.

    However, the datasheet says that the CLK_QUAL_DIS setting…