Can you confirm that you are all set or not?
Thanks your reply was helpful in finding the problem. It turns out the problem with the setup of the SPI port
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; // caused the readout to miss the MSB
The change below resolved it
hspi1.Init.CLKPolarity = SPI_…
My question would be a very simple question. I'm asking because I can't perceive it because I'm a student.
I intend to connect Raspberry pi with AD7767. However, I can't be sure which data pins of the AD7767 are MOSI, MISO, SCLK and CS…
Reading the AD7767 data sheet Absolute Maximum Ratings, it appears that it is possible to have power on the VDRIVE pin, but none on the AVdd, DVdd and Vref.
Is this correct?
I am designing a board where it may be that during initial programming, there…
I have a AD7767 evaluation board. When I test INL, I have the following interface. What is the matter?Fin=324.25Hz,Other conditions are default.
I will use AD7767 DAISY-CHAIN MODE
I'd like to confirm only that a DRDY signal becomes Low first, so SCLK isn't kept.
A DRDY signal won't be Low only AD7767 (A), is SCLK necessary?
（SCLK is being always input in figure 37, but is it necessary…