AD7767主时钟由STM32提供80KHz时，DRDY信号产生异常，2S以上才产生一个DRDY信号，使用外部信号发生器提供80KHz时钟时，DRDY信号正常，请问这是什么问题？
Hi jcorao-san,
Thank you for your comment.
Now I understood that the decimation rate of AD7767, AD7767-1 and AD7767-2 are fixed.
I will choose different type listed in the data sheet which you suggested.
Thank you for your help,
Ricky
Hi Sreeni,
It really depends on the bandwidth of your measurement, power and the dynamic range you require.
From the precision ADCs the AD7767, AD7767-1,AD7767-2 are devices which have been used for high dynamic range frequency analysis hook up to…
AD7767: How is the maximun input current on the VREF Pin?
I will use AD7767 DAISY-CHAIN MODE
I'd like to confirm only that a DRDY signal becomes Low first, so SCLK isn't kept.
A DRDY signal won't be Low only AD7767 (A), is SCLK necessary?
（SCLK is being always input in figure 37, but is it necessary…
Hello together
I have the Eval Board of the AD7767. Now I try to measure the SNR of the AD7767, but I get all the time 6 time higher values than in the Datasheet.
I have shorted the Input of the ADC.
So my question is about the SNR, is this based on…
ad7766和ad7767有什么区别？
Hi Johnny
I tried your filter settings with 15Ohms serial and the 2,2nF to GND. 10nF was removed. The result looks very bad. Linearity error increase to 2%. Seems that my opamp isn't able to drive the ADC.
I try to find another one with higher…
Hi, Tak.
You do need a continuous MCLK signal on initial powerup. Synchronization features are implemented relative to the rising edges of MCLK. This is shown on Figure 5 of the AD7767-1 datasheet. The settling time is also a function of the MCLK frequency…
Hi Ajith Peter,
The AD7767 is a differential ADC, the input that the ADC is converting is the difference of the two inputs Ain+ and Ain- which the result of the difference ranges from +/-Vref. But another parameter that need to consider is the common…