AD7767主时钟由STM32提供80KHz时，DRDY信号产生异常，2S以上才产生一个DRDY信号，使用外部信号发生器提供80KHz时钟时，DRDY信号正常，请问这是什么问题？

Hi

I'm using the AD7767 for a high precision measuring device. There is an input stage that reduces my input voltage from +/-12V to +/-2,4V and a Diff Amp to drive the ADC. My ADC input filter consists of two 15 Ohm resistors and one 10nF capacitor.…

Hello together

I have the Eval Board of the AD7767. Now I try to measure the SNR of the AD7767, but I get all the time 6 time higher values than in the Datasheet. 

I have shorted the Input of the ADC.

So my question is about the SNR, is this based on…

Hello everybody,

In the AD7767 datasheet (rev C) the value Tsettling in the table on page 5 of 24 is specified as:

(592 × n) + 2 in mclk cycles. (digital filter settling time plus 2 mclk cycles for power-up and reset I assume)

For the AD7767-2, n …

Hi,

I want to implement the AD7767 in a board.

can I use the device without connecting the DRDY line?

I cannot find in the datasheet any information regarding the conversion time, please advice.

Thank you,

Amir

Reading the AD7767 data sheet Absolute Maximum Ratings, it appears that it is possible to have power on the VDRIVE pin, but none on the AVdd, DVdd and Vref.

Is this correct?

I am designing a board where it may be that during initial programming, there…

Hi,

I would like to know: what's the max SPI speed for the AD7767? 

I've been trying to acquire data from a load cell using the AD7767 along with an ESP32; the problem is that once every few batches of data a 0 occurs on the serial interface and…

AD7767的Datasheet中关于CMRR的定义为：

满量程频率f下ADC输出功率与频率fs下施加于共模输入电压VIN+和VIN−的100 mV正弦波功率的比值。

CMRR (dB) = 10 log(Pf/Pfs)

其中，Pf是频率f下的ADC输出功率，Pfs是频率fs下的ADC输出功率。

是否可以如下理解：

1、以频率范围内的任何频率f，生成100mV的差模信号Vd；

2、以频率范围内的任何频率fs，生成100mV的共模模信号Vc;

3、f<>fs;

把Vd+Vc施加到AD7767的输出端…

I will use AD7767 DAISY-CHAIN MODE

I'd like to confirm only that a DRDY signal becomes Low first, so SCLK isn't kept.

A DRDY signal won't be Low only AD7767 (A), is SCLK necessary?

（SCLK is being always input in figure 37, but is it necessary…

I have a AD7767 evaluation board. When I test INL, I have the following interface. What is the matter?Fin=324.25Hz,Other conditions are default.