• AD7766 reliability data

    Hello AD,

    can you please provide me with the MTTF/FIT data for AD7766 (if available)? If not, can you please give me a hint, which simillar part should I fill in your MTTF calculator?
    Every input is appreciated...

    Thank you very much
    Regards Martin

  • AD7766

    I am using AD7766 (24bit at 128kSPS). I need to use the digital filter and have filter pass band frequency variable (from 10 HZ to 50 kHZ). This corresponds to 0.547 x ODR. I implemented the scheme where in I am changing FMCLK accordingly. For AD7766…

  • AD7766 Evaluation Board

    Is there any type of interposer card that can support the AD7766 evaluation board to an FMC type of connection? I am trying to connect the evaluation board to an FPGA evaluation board that supports an FMC interface.

  • AD7766-2 Flatline

    We are using two AD7766-2 ADCs in our application, read by an FPGA.  We've seen very occasionally (<1%) where one channel will not initialize properly and never trigger DRDY.  Toggling the SYNC/PD lines does not solve the problem.  Has anyone seen…

  • AD7766, ADG1606

    Dear sir

    I want to use AD7766 to convert 16ch. (maybe 32) analogue input to digital.

    First question:

    To do that, I need an analogue MUX, concerning to noise and leakage current,  ADG1606 is a good choice or no ? if no, can you propose an analogue…

  • AD7766 minimum clock MCLK

    AD7766 is specified with a maximum clock MCLK = 1.024 MHz. What is the minimum
    clock frequency of MCLK?


    There is no min on the MCLK required for the AD7766.
  • AD7766 Phase response


    I am using AD7766 to digitize a reference AWG signal from 0.1 to 50Hz.

    When I plot the output of AD7766, I see a the digitized samples has a changing phase delay relative to input frequency.

    The delay appears to be from 45 degrees to 70+ degrees…

  • AD7766 linux driver


    I am attempting to get the Analog Devices AD7766 driver working on a Humming Board (quad imx6). From the device tree sample that I was given, I am assuming that the AD7766 /DRDY is connected to a GPIO and that interrupts from this GPIO are hooked…

  • AD7766 Reset condition


    Please let me ask as an additional question for Number of MCLK to make AD7766 reset 

    How long should the / SYNC signal keep low level to reset the AD7766?

    Or, after /SYNC move high to low, how many MCLK should need before move the /SYNC to HIgh…

  • AD7766 full scale ?

    Hello all !

    I use AD7766-2 converter in my project

    I apply 5v at Vref+ input from ADR435, and use common mode voltage Vref/2=2.5v.

    I checked that Vref/2 in +-5% range!!!

    And I apply diff  sin signal (peak to peak) 2.6v p-p   around 2.5v (Vref/2)  to inputs…