I can read up to 70 samples consistently. Anything greater than 70 results in a timeout.
iio_readdev -t ad7766-dev0 -s 70 -b 70 iio:device0
Here is my debug when reading one sample using iio_readdev
[ 4615.492787] ad7766 read raw
I am using AD7766 (24bit at 128kSPS). I need to use the digital filter and have filter pass band frequency variable (from 10 HZ to 50 kHZ). This corresponds to 0.547 x ODR. I implemented the scheme where in I am changing FMCLK accordingly. For AD7766…
The reference project for AD7766 is now available on the wiki at the following location:
hey, I am using ced1z with ad7766, I need to give one more input "A" to the ced1z/adc, so as to raise the flag/tag at the output. How do I do it?
I believe I should be using SPI interfacing as AD7766 uses SPI, if not plz guide.
Also plz tell…
Thanks for the question. As mentioned, the Abs max is -0.3V to 6V, this means that the 5V Vdrive is within the abs max and this should not damage the AD7766.
The AD7766 specifications, as noted in table 2, was guaranteed at Vdrive …
The reset of the AD7766 is through the SYNC/PD pin. After the falling edge of SYNC/PD pin, the first MCLK rising edge, the AD7766 is in power down. At this time the DRDY pin will go high to indicate that the data in the SDO are invalid. The…
I am using AD7766 to digitize a reference AWG signal from 0.1 to 50Hz.
When I plot the output of AD7766, I see a the digitized samples has a changing phase delay relative to input frequency.
The delay appears to be from 45 degrees to 70+ degrees…