I am using AD7765 EVAL Board with Artix-7 FPGA board.
MCLK - 40MHz on board crystal available on EVAL AD7765 Board.
DEC Rate - 128x with ODR = 156.2kHz.
I am giving 1VDC input from voltage source to Pin 2 (+ve) and Pin 3 (-ve) of J1 Connector on…
We have an AD7765EDZ board which we want to connect to our FPGA. We want to use the SPI instead of SPORT, is that possible? To work without EVAL-CED1Z we changed the 0 Ohm resistor from R11 to R29 position. Can you suggest us some connection…
I am about to use AD7765 and i am confused with max input signal level for differential amp.
The datasheet on page 18 says :
The common-mode input at each of the differential amplifier inputs (Pin VINA+ and Pin VINA−) can range from−0.5 V dc to
I have a board that is daisy chaining 4x AD7765's and have it happily working in DEC_RATE = 0 (256x), BUT I cannot get 128x to work correctly.
Q1: What level do I set DEC_RATE to 128x? Do I drive it high or set it floating?
Here is a trace of it…
#define SCO PBin(4) //在单片机看来是输入，AD是输出
#define SDI PCout(12) //在单片机看来是输出，AD是输入
#define FSI PCout(11)
#define FSO PBin(3)
#define RSET PCout(10)
#define PA0 PAout(0)
u32 temp = 0;
SCK = 0；
FSO = 1;
SCK = 1;
SYNC = 0;
SCK = 0;
SCK = 1;
May I know exactly what is your application and why do you need to synchronized DAC with the ADC? AD7765 has a /SYNC pin which allows the user to control the start of conversion/gathering samples from a known point in time. When this pin is low…
the REFGND pin of the AD7765 must be tied to AGND. It cannot be tied to a voltage above ground as can be done with the AD7195.