I am using AD7765 EVAL Board with Artix-7 FPGA board.
MCLK - 40MHz on board crystal available on EVAL AD7765 Board.
DEC Rate - 128x with ODR = 156.2kHz.
I am giving 1VDC input from voltage source to Pin 2 (+ve) and Pin 3 (-ve) of J1 Connector on…
the REFGND pin of the AD7765 must be tied to AGND. It cannot be tied to a voltage above ground as can be done with the AD7195.
I have a board that is daisy chaining 4x AD7765's and have it happily working in DEC_RATE = 0 (256x), BUT I cannot get 128x to work correctly.
Q1: What level do I set DEC_RATE to 128x? Do I drive it high or set it floating?
Here is a trace of it…
Changing the clock source to come from the crystal oscillator takes care of the MCLK signal source.
This MCLK is the core clock to run the ADC conversions and also times the output data rate signal FSO and the data clock SCO.
u32 temp = 0;
SCK = 0；
FSO = 1;
SCK = 1;
SYNC = 0;
SCK = 0;
SCK = 1;
I am about to use AD7765 and i am confused with max input signal level for differential amp.
The datasheet on page 18 says :
The common-mode input at each of the differential amplifier inputs (Pin VINA+ and Pin VINA−) can range from−0.5 V dc to
May I know exactly what is your application and why do you need to synchronized DAC with the ADC? AD7765 has a /SYNC pin which allows the user to control the start of conversion/gathering samples from a known point in time. When this pin is low…