• AD7762 MCLK buffering requirements

    . what is the minimum voltage required for the clock input (MCLK). I'm using a Crystal and gate buffer as per ad7760 evaluation board design, frequency is accurate but the max voltage of the clock source is 2v.

    data sheets show MCLK voltage to be…

  • Your conditions of AD7762

    Dear Sir/Madam,

    Our customer asked  as following questions.

    He cannot find the condition on your datasheet.


    What is the condition of set/reset for DVALID bit status register?


    What is the condition of set/reset for OVR bit status register…

  • AD7760/AD7762 Evaluation Board

    Dear Community,

    Could I ask two questions of AD7760/AD7762?

    1. Can I connect it with my own ARM development board with standard ports like I2C, SPI?

    2. What is the precision of this board? The ADC is a 24-bit one. However, it shows in the website…

  • RE: Question for your AD7762

    Hi Kaos,

         The AD7762 minimum VOH is 1.5V at 400uA .If there would be changes on the load current , I think the VOH would still be a range around 1.5V to around Vdrive level which is the supply for the interface of the AD7762. I'll check if I can find…

  • Use as daisy chain AD7762

    Dear Sir/Madam,


    Your datasheet page 17 show "Take SYNC low for a minimum of 4 MCLK cycles, if

    required, to synchronize multiple parts."

    As for the AD7762 internal working,

    after get the /SYNC L to H edge, your ADC start to work, correct…

  • AD7762 Analog DC Input Current


    In the datasheet, there is no information about the dc input current of the analog pins (VinA+, VinA-, Vin+, Vin-) of the AD7762. I can measure a input current of about 600 uA at Vin+ and Vin-, dependant to the input voltage (higher input voltage…

  • AD7762 input maximums when power OFF


    I discovered some issues with my AD7762 design and I don't have enough info from the chip to know how to tackle it.

    In summary, I need to have my circuit capable of receiving the full input signal while not being powered ON without being damaged…

  • AD7762 - Suitable FIFO buffer for interfacing


    Can someone please recommend a fast high-speed PARALLEL INPUT FIFO buffer with a serial output using SPI that I can use to interface with the AD7762 ADC?


    I am looking for…

  • A suitable interface device for AD7762


    I would like to select the suitable interface device, as level translator to 3.3V, for AD7762.

    An interface device's Vinh min is mostly 0.7 or 0.65 X Vdd min, I think.

    It is about 1.65V at vdd=2.5V.

    But AD7762/3 's Voh is 1.5V min.


  • AD7762 Timing at parallel bus

    at parallel bus, is it really true, that register address and register data must be stable before the falling edge of /CS (t11 at Fig.3)? It is an unusual timing and then it's not possible to control an isolating bus buffer by the same /CS. Please…